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Inventor

Michitaka Okuno

Inventor
Kokubunji, JP

Overview

23→
Patents
2005–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication52%
G06FElectric digital data processing31%
H04QSelecting7%
H04JMultiplex communication3%
H04WWireless communication networks3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
9,769,265'Communication system, management computer, and session information migration method'20179,600,380'Failure recovery system and method of creating the failure recovery system'20179,535,730'Communication apparatus and configuration method'20179,521,056'Communication system'20169,407,459'Communication apparatus, communication system, and communication method to transmit and receive Ethernet frames'20169,294,342'Network node apparatus system, apparatus, and method'20168,868,998'Packet communication apparatus and packet communication method'20148,798,051'Information and communication processing system, method, and network node'20148,782,239'Distributed router computing at network nodes'20148,401,384'Optical access system, optical switching unit and optical line terminal'20138,380,065'Optical access system and optical line terminal'20138,135,004'Multi-plane cell switch fabric system'20128,116,305'Multi-plane cell switch fabric system'20128,095,721'Network switch and method of switching in network'20127,907,606'Multi-plane cell switch fabric system'20117,656,887'Traffic control method for network equipment'20107,630,373'Packet transfer apparatus'20097,529,251'Data transfer device'20097,440,457'Network-processor accelerator'20087,051,177'Method for measuring memory latency in a hierarchical memory system'20067,047,398'Analyzing instruction completion delays in a processor'20066,970,999'Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters'20056,910,120'Speculative counting of performance events with rewind counter'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2006Patents assigned to IBM (4)· patent assignee history
2005–2006Based in Nagano, JP· patent location history
2008–2017Patents assigned to HITACHI LTD (16)· patent assignee history
2008–2017Based in Tokyo, JP· patent location history
2009–2016Based in Kokubunji, JP· patent location history
2011–2012Patents assigned to ALAXALA NETWORKS CORP (3)· patent assignee history
2012–2016Patents assigned to OKUNO MICHITAKA (8)· patent assignee history
2014–2016Patents assigned to YAZAKI TAKEKI (3)· patent assignee history
2014Based in Kobubunji, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HITACHI LTD162008–2017
OKUNO MICHITAKAself82012–2016
IBM42005–2006
ALAXALA NETWORKS CORP32011–2012
YAZAKI TAKEKI32014–2016
Locations
LocationPatentsSpan
Kokubunji, JP122009–2016
Tokyo, JP62008–2017
Nagano, JP42005–2006
Kobubunji, JP12014