Inventor

Allen S. Yu

Inventor

Fremont, CA, US

Overview

1999–2006

Patent span

Electricity

Primary field (CPC H)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1035%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%

H10DInorganic electric semiconductor devices18%

H10BElectronic memory devices6%

G01RMeasuring electric variables4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%

G01NInvestigating or analysing materials by determining their chemical or physical properties2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%

G06TImage data processing or generation, in general2%

G06FElectric digital data processing1%

PatentTitleYear

7,033,919'Fabrication of dual work-function metal gate structure for complementary field effect transistors'2006 6,864,163'Fabrication of dual work-function metal gate structure for complementary field effect transistors'2005 6,709,924'Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate'2004 6,605,541'Pitch reduction using a set of offset masks'2003 6,596,591'Methods to form reduced dimension bit-line isolation in the manufacture of non-volatile memory devices'2003 6,524,916'Controlled gate length and gate profile semiconductor device and manufacturing method therefor'2003 6,512,842'Composition based association engine for image archival systems'2003 6,506,639'Method of forming low resistance reduced channel length transistors'2003 6,468,815'Overlay radius offset shift engine'2002 6,463,171'Automatic defect resizing tool'2002 6,448,606'Semiconductor with increased gate coupling coefficient'2002 6,433,371'Controlled gate length and gate profile semiconductor device'2002 6,430,572'Recipe management database system'2002 6,426,301'Reduction of via etch charging damage through the use of a conducting hard mask'2002 6,424,881'Computer generated recipe selector utilizing defect file information'2002 6,423,557'ADC based in-situ destructive analysis selection and methodology therefor'2002 6,421,574'Automatic defect classification system based variable sampling plan'2002 6,395,567'Process control using ideal die data in an optical comparator scanning system'2002 6,387,758'Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material'2002 6,377,898'Automatic defect classification comparator die selection system'2002 6,376,877'Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor'2002 6,376,312'Formation of non-volatile memory device comprised of an array of vertical field effect transistor structures'2002 6,369,453'Semiconductor wafer for measurement and recordation of impurities in semiconductor insulators'2002 6,350,639'Simplified graded LDD transistor using controlled polysilicon gate profile'2002 6,338,001'In line yield prediction using ADC determined kill ratios die health statistics and die stacking'2002 6,303,394'Global cluster pre-classification methodology'2001 6,291,332'Electroless plated semiconductor vias and channels'2001 6,291,252'Automatic method to eliminate first-wafer effect'2001 6,287,968'Method of defining copper seed layer for selective electroless plating processing'2001 6,287,922'Method for fabricating graded LDD transistor using controlled polysilicon gate profile'2001 6,284,553'Location dependent automatic defect classification'2001 6,274,443'Simplified graded LDD transistor using controlled polysilicon gate profile'2001 6,272,393'Efficient tool utilization using previous scan data'2001 6,261,960'High density contacts having rectangular cross-section for dual damascene applications'2001 6,238,940'Intra-tool defect offset system'2001 6,239,008'Method of making a density multiplier for semiconductor device manufacturing'2001 6,214,742'Post-via tin removal for via resistance improvement'2001 6,204,133'Self-aligned extension junction for reduced gate channel'2001 6,200,823'Method for isolation of optical defect images'2001 6,191,036'Use of photoresist focus exposure matrix array as via etch monitor'2001 6,191,044'Method for forming graded LDD transistor using controlled polysilicon gate profile'2001 6,177,287'Simplified inter database communication system'2001 6,171,874'Non-defect image and data transfer and storage methodology'2001 6,165,805'Scan tool recipe server'2000 6,133,140'Method of manufacturing dual damascene utilizing anisotropic and isotropic properties'2000 6,107,204'Method to manufacture multiple damascene by utilizing etch selectivity'2000 6,103,616'Method to manufacture dual damascene structures by utilizing short resist spacers'2000 6,100,593'Multiple chip hybrid package using bump technology'2000 6,093,647'Method to selectively electroplate conductive material into trenches'2000 6,091,138'Multi-chip packaging using bump technology'2000 6,084,679'Universal alignment marks for semiconductor defect capture and analysis'2000 6,025,272'Method of planarize and improve the effectiveness of the stop layer'2000 6,025,259'Dual damascene process using high selectivity boundary layers'2000 6,013,570'LDD transistor using novel gate trim technique'2000 5,985,753'Method to manufacture dual damascene using a phantom implant mask'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2005Patents assigned to ADVANCED MICRO DEVICES INC (54)· patent assignee history

1999–2006Based in Fremont, CA, US· patent location history

2006Patents assigned to PAN JAMES (1)· patent assignee history

2006Patents assigned to YU ALLEN S (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	54	1999–2005
PAN JAMES	1	2006
YU ALLEN Sself	1	2006

Locations

Location	Patents	Span
Fremont, California, US	55	1999–2006