Inventor
Atila Alvandpour
Inventor
Portland, OR, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique39%
G11CStatic stores35%
G01RMeasuring electric variables6%
G06FElectric digital data processing6%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
H03FAmplifiers3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
7,053,663'Dynamic gate with conditional keeper for soft error rate reduction'20067,002,389'Fast static receiver with input transition dependent inversion threshold'20066,919,737'Voltage-level converter'20056,847,569'Differential current sense amplifier'20056,838,910'Fast dual-rail dynamic logic style'20056,791,364'Conditional burn-in keeper for dynamic circuits'20046,751,141'Differential charge transfer sense amplifier'20046,717,441'Flash II-Domino: a fast dual-rail dynamic logic style'20046,707,708'Static random access memory with symmetric leakage-compensated bit line'20046,690,205'Enhanced domino circuit'20046,633,190'Multi-phase clock generation and synchronization'20036,617,890'Measuring power supply stability'20036,614,680'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,590,801'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,559,492'On-die switching power converter with stepped switch drivers and method'20036,549,040'Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates'20036,519,178'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,510,077'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,498,514'Domino circuit'20026,493,254'Current leakage reduction for loaded bit-lines in on-chip memory structures'20026,388,940'Leakage-tolerant circuit and method for large register files'20026,353,342'Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission'20026,351,150'Low switching activity dynamic driver for high performance interconnects'20026,137,319'Reference-free single ended clocked sense amplifier circuit'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2006Patents assigned to INTEL CORP (24)· patent assignee history
2000–2006Based in Linkoping, SE· patent location history
2002–2006Based in Portland, OR, US· patent location history
2004Based in Beaverton, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 24 | 2000–2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 20 | 2002–2006 |
| Linkoping, SE | 2 | 2000–2006 |
| Beaverton, OR, US | 2 | 2004 |