Inventor
Suresh V. Golwalkar
Inventor
Phoenix, AZ, US
Overview
Patents· 13 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G02Bprimary
G02BOptical elements, systems or apparatus20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
Y10TTechnical subjects covered by former us classification12%
A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing8%
G01PMeasuring linear or angular speed, acceleration, deceleration, or shock8%
G09BEducational or demonstration appliances8%
B29CShaping or joining of plastics4%
B29LIndexing scheme associated with subclass b29c, relating to particular articles4%
G06KGraphical data reading4%
G10HElectrophonic musical instruments4%
PatentTitleYear
10,960,285Sensor-derived object flight performance tracking202110,420,999Sensor-derived object flight performance tracking201910,049,650Ultra-wide band (UWB) radio-based object sensing20187,476,037'Apparatus for coupling a fiber optic cable to an optoelectronic device, a system including the apparatus, and a method of forming the same'20097,101,091'Apparatus for coupling a fiber optic cable to an optoelectronic device, a system including the apparatus, and a method of forming the same'20067,002,249'Microelectronic component with reduced parasitic inductance and method of fabricating'20066,960,031'Apparatus and method of packaging two dimensional photonic array devices'20056,850,658'Apparatus for coupling an optoelectronic device to a fiber optic cable and a microelectronic device, a system including the apparatus, and a method of forming the same'20056,786,651'Optical interconnect structure, system and transceiver including the structure, and method of forming the same'20045,545,922'Dual sided integrated circuit chip package with offset wire bonds and support block cavities'19965,527,740'Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities'19965,366,933'Method for constructing a dual sided, wire bonded integrated circuit chip package'19945,336,456'Method of producing a scribelined layout structure for plastic encapsulated circuits'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2021Patents assigned to INTEL CORP (7)· patent assignee history
1994–1996Based in Folsom, CA, US· patent location history
1994Based in Orangevale, CA, US· patent location history
2004–2006Patents assigned to PRIMARION INC (4)· patent assignee history
2004–2021Based in Phoenix, AZ, US· patent location history
2006–2009Patents assigned to ZARLINK SEMICONDUCTOR INC (2)· patent assignee history
2018Based in Chandler, AZ, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 7 | 1994–2021 |
| PRIMARION INC | 4 | 2004–2006 |
| ZARLINK SEMICONDUCTOR INC | 2 | 2006–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Phoenix, AZ, US | 8 | 2004–2021 |
| Folsom, California, US | 3 | 1994–1996 |
| Chandler, AZ, US | 1 | 2018 |
| Orangevale, California, US | 1 | 1994 |