Inventor
Yaron Slezak
Inventor
Raanana, IL
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication19%
G09GArrangements or circuits for control of indicating devices using static means to present variable information13%
G11CStatic stores13%
G05FSystems for regulating electric or magnetic variables6%
G06FElectric digital data processing6%
H02JElectric power networks6%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems6%
G01RMeasuring electric variables3%
H01RElectrically-conductive connections3%
H03GControl of amplification3%
PatentTitleYear
9,423,812'Current mode boost converter using slope compensation'20169,288,065'Techniques for protecting digital multimedia interfaces'20169,197,023'Apparatus for enabling simultaneous content streaming and power charging of handheld devices'20158,949,481'Techniques for achieving complete interoperability between different types of multimedia display interfaces'20158,886,852'Techniques for achieving complete interoperability between different types of data and multimedia interfaces in handheld devices'20148,878,590'Techniques for switching between AC-coupled connectivity and DC-coupled connectivity'20148,837,573'Apparatus and method thereof for compensating for gain changes of N-PAM modulate signals'20148,804,809'Techniques for setting feedback coefficients of a PAM-N decision feedback equalizer'20148,594,262'Apparatus and method thereof for clock and data recovery of N-PAM encoded signals using a conventional 2-PAM CDR circuit'20138,576,903'Techniques for adaptively adjusting decision levels of a PAM-N decision feedback equalizer'20138,222,874'Current mode boost converter using slope compensation'20126,628,173'Data and clock extractor with improved linearity'20036,430,719'General port capable of implementing the JTAG protocol'20026,243,842'Method and apparatus for operating on a memory unit via a JTAG port'20015,719,818'Row decoder having triple transistor word line drivers'19985,696,730'First read cycle circuit for semiconductor memory'19975,682,353'Self adjusting sense amplifier clock delay circuit'19975,511,032'Source pre-charge system in a memory array'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–1998Patents assigned to WAFERSCALE INTEGRATION INC (4)· patent assignee history
1996Based in Haifa, IL· patent location history
1997–2002Based in Kiryat Motzkin, IL· patent location history
2003–2015Based in Ra'anana, IL· patent location history
2012–2016Patents assigned to SLEZAK YARON (10)· patent assignee history
2012–2016Based in Raanana, IL· patent location history
2013–2014Patents assigned to TRANSWITCH CORP (5)· patent assignee history
2014–2016Patents assigned to CADENCE DESIGN SYSTEMS INC (5)· patent assignee history
2014–2015Patents assigned to BAR-NIV AMIR (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SLEZAK YARONself | 10 | 2012–2016 |
| CADENCE DESIGN SYSTEMS INC | 5 | 2014–2016 |
| TRANSWITCH CORP | 5 | 2013–2014 |
| WAFERSCALE INTEGRATION INC | 4 | 1996–1998 |
| BAR-NIV AMIR | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Raanana, IL | 7 | 2012–2016 |
| Ra'anana, IL | 5 | 2003–2015 |
| Kiryat Motzkin, IL | 5 | 1997–2002 |
| Haifa, IL | 1 | 1996 |