Inventor
Ian A. Swarbrick
Inventor
Santa Clara, CA, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing50%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
H04LTransmission of digital information, e.g. telegraphic communication12%
H03KPulse technique11%
G11CStatic stores8%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%
H04WWireless communication networks1%
PatentTitleYear
11,063,594Adaptive integrated programmable device platform202110,963,421Flexible address mapping for a NoC in an integrated circuit202110,936,486Address interleave support in a programmable device202110,893,005Partial reconfiguration for Network-on-Chip (NoC)202110,838,908Configurable network-on-chip for a programmable device202010,824,505ECC proxy extension and byte organization for multi-master systems202010,817,455Peripheral I/O device with assignable I/O and coherent domains202010,680,615Circuit for and method of configuring and partially reconfiguring function blocks of an integrated circuit device202010,673,439Adaptive integrated programmable device platform202010,673,745End-to-end quality-of-service in a network-on-chip202010,628,547Routing circuit designs for implementation using a programmable network on chip202010,621,129Peripheral interconnect for configurable slave endpoint circuits202010,621,132Auto address generation for switch network202010,503,690Programmable NOC compatible with multiple interface communication protocol201910,503,657DIMM SSD Addressing performance techniques201910,505,548Multi-chip structure having configurable network-on-chip201910,346,346Inline ECC function for system-on-chip201910,243,882Network on chip switch interconnect201910,121,013XOR-based scrambler/descrambler for SSD communication protocols201810,062,422Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets201810,031,674DIMM SSD addressing performance techniques201810,025,747I/O channel scrambling/ECC disassociated communication protocol20189,495,290'Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering'20169,489,304'Bi-domain bridge enhanced systems and communication methods'20169,292,436'Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary'20169,264,368'Chip-to-chip communications'20169,264,030'Adaptive voltage scaling using a delay line'20168,949,474'Method for inter-chip and intra-chip addressing using port identifiers and address mapping'20158,826,047'Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers'20148,717,089'Adaptive voltage scaling using a delay line'20148,519,781'Adaptive voltage scaling using a delay line'20138,448,001'System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device'20138,407,433'Interconnect implementing internal controls'20138,378,738'Adaptive voltage scaling using a delay line'20138,024,697'Various methods and apparatuses for estimating characteristics of an electronic systems design'20117,694,249'Various methods and apparatuses for estimating characteristics of an electronic system\'s design'20107,290,162'Clock distribution system'20077,149,829'Various methods and apparatuses for arbitration among blocks of functionality'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2018Patents assigned to SONICS INC (7)· patent assignee history
2006–2016Based in Sunnyvale, CA, US· patent location history
2013–2016Patents assigned to MARVELL INT LTD (8)· patent assignee history
2013–2018Patents assigned to SWARBRICK IAN (4)· patent assignee history
2013–2021Based in Santa Clara, CA, US· patent location history
2018–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (4)· patent assignee history
2019–2021Patents assigned to XILINX INC (17)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 17 | 2019–2021 |
| MARVELL INT LTD | 8 | 2013–2016 |
| SONICS INC | 7 | 2006–2018 |
| SAMSUNG ELECTRONICS CO LTD | 4 | 2018–2019 |
| SWARBRICK IANself | 4 | 2013–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 27 | 2013–2021 |
| Sunnyvale, California, US | 11 | 2006–2016 |