Inventor
Daxin Mao
Inventor
Cupertino, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10BElectronic memory devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10DInorganic electric semiconductor devices10%
B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool4%
B24BMachines, devices, or processes for grinding or polishing3%
C09GPolishing compositions1%
C25FProcesses for the electrolytic removal of materials from objects1%
G11CStatic stores1%
PatentTitleYear
10,354,956Three-dimensional memory device containing hydrogen diffusion barrier structures for CMOS under array architecture and method of making the same201910,269,620Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof201910,256,248Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof201910,249,640Within-array through-memory-level via structures and method of making thereof201910,217,746Three-dimensional memory device having L-shaped word lines and a support structure and methods of making the same201910,115,732Three dimensional memory device containing discrete silicon nitride charge storage regions201810,056,399Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same201810,008,570Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device20189,985,046Method of forming a staircase in a semiconductor device using a linear alignment control feature20189,859,363'Self-aligned isolation dielectric structures for a three-dimensional memory device'20189,853,043Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material20179,728,551'Multi-tier replacement memory stack structure integration scheme'20179,716,101'Forming 3D memory cells after word line replacement'20179,679,906'Three-dimensional memory devices containing memory block bridges'20179,673,213'Three dimensional memory device with peripheral devices under dummy dielectric layer stack and method of making thereof'20179,543,318'Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors'20179,449,987'Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors'20168,337,279'Closed-loop control for effective pad conditioning'20127,879,255'Method and composition for electrochemically polishing a conductive material on a substrate'20117,582,564'Process and composition for conductive material removal by electrochemical mechanical polishing'20097,210,988'Method and apparatus for reduced wear polishing pad conditioning'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2012Patents assigned to APPLIED MATERIALS INC (4)· patent assignee history
2007–2019Based in Cupertino, CA, US· patent location history
2012Patents assigned to CHANG SHOU-SUNG (1)· patent assignee history
2012Patents assigned to CHEN HUNG CHIH (1)· patent assignee history
2012–2017Based in San Jose, CA, US· patent location history
2016–2019Patents assigned to SANDISK TECHNOLOGIES LLC (17)· patent assignee history
2016–2018Patents assigned to SANDISK TECHNOLOGIES INC (8)· patent assignee history
2017Based in Milpitas, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 17 | 2016–2019 |
| SANDISK TECHNOLOGIES INC | 8 | 2016–2018 |
| APPLIED MATERIALS INC | 4 | 2007–2012 |
| CHANG SHOU-SUNG | 1 | 2012 |
| CHEN HUNG CHIH | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 18 | 2007–2019 |
| San Jose, California, US | 2 | 2012–2017 |
| Milpitas, California, US | 1 | 2017 |