Inventor
Kuiwon KANG
Inventor
US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H01LSemiconductor devices38%
H05KPrinted circuits11%
H10DInorganic electric semiconductor devices4%
H10BElectronic memory devices2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H10NElectric solid-state devices not otherwise provided for2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
PatentTitleYear
12,593,408Package substrate having embedded electronic component in a core of the package substrate202612,581,966Electronic component placed on core of substrate202612,500,146Substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength, and related IC packages and fabrication methods202512,424,559Package with a substrate comprising embedded escape interconnects and surface escape interconnects202512,362,269Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods202512,354,935Integrated circuit (IC) package substrate with embedded trace substrate (ETS) layer on a substrate, and related fabrication methods202511,791,320Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods202311,776,888Package with a substrate comprising protruding pad interconnects202311,764,076Semi-embedded trace structure with partially buried traces202311,676,905Integrated circuit (IC) package with stacked die wire bond connections, and related methods202311,637,057Uniform via pad structure having covered traces between partially covered pads202311,605,595Packages with local high-density routing region embedded within an insulating layer202311,552,015Substrate comprising a high-density interconnect portion embedded in a core layer202311,552,023Passive component embedded in an embedded trace substrate (ETS)202311,545,435Double sided embedded trace substrate202311,545,439Package comprising an integrated device coupled to a substrate through a cavity202311,527,498Bump pad structure202211,444,019Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package202211,437,335Integrated circuit (IC) packages employing a thermal conductive package substrate with die region split, and related fabrication methods202211,404,343Package comprising a substrate configured as a heat spreader202211,342,254Multi-dielectric structure in two-layer embedded trace substrate2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to QUALCOMM INC (21)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 21 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 21 | 2022–2026 |