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Inventor

Farrell Good

Inventor
Meridian, ID, US

Overview

20→
Patents
2001–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices20%
H10DInorganic electric semiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01LSemiconductor devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
H10NElectric solid-state devices not otherwise provided for6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y10TTechnical subjects covered by former us classification6%
G11CStatic stores5%
C23CCoating metallic material3%
PatentTitleYear
11,084,163Mobile project center system202110,879,462Devices including multi-portion liners202010,665,782Methods of forming semiconductor structures including multi-portion liners202010,658,580Semiconductor structures including multi-portion liners202010,249,819Methods of forming semiconductor structures including multi-portion liners20198,980,752'Method of forming a plurality of spaced features'20158,492,278'Method of forming a plurality of spaced features'20138,476,002'Methods of forming patterned masks'20138,450,164'Methods of forming a plurality of capacitors'20138,318,578'Method of forming capacitors'20128,288,083'Methods of forming patterned masks'20127,682,924'Methods of forming a plurality of capacitors'20107,618,874'Methods of forming capacitors'20097,550,340'Silicon rich barrier layers for integrated circuit devices'20097,405,447'Silicon rich barrier layers for integrated circuit devices'20087,211,479'Silicon rich barrier layers for integrated circuit devices'20077,071,049'Silicon rich barrier layers for integrated circuit devices'20066,903,425'Silicon rich barrier layers for integrated circuit devices'20056,537,910'Forming metal silicide resistant to subsequent thermal processing'20036,210,813'Forming metal silicide resistant to subsequent thermal processing'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2020Patents assigned to MICRON TECHNOLOGY INC (19)· patent assignee history
2001–2013Based in Boise, ID, US· patent location history
2005–2020Based in Meridian, ID, US· patent location history
2012–2013Patents assigned to GOOD FARRELL (5)· patent assignee history
2012–2013Patents assigned to BHAT VISHWANATH (2)· patent assignee history
2012–2013Patents assigned to CARR ROBERT (2)· patent assignee history
2012–2013Patents assigned to ZHANG ZISHU (2)· patent assignee history
2019Based in Meridan, ID, US· patent location history
2021Based in Ogden, IA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC192001–2020
GOOD FARRELLself52012–2013
BHAT VISHWANATH22012–2013
CARR ROBERT22012–2013
ZHANG ZISHU22012–2013
Locations
LocationPatentsSpan
Meridian, ID, US152005–2020
Boise, ID, US32001–2013
Ogden, IA, US12021
Meridan, ID, US12019