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Inventor

Kishore Ven Kasamsetty

Inventor
Cupertino, CA, US

Overview

24→
Patents
2006–2020
Patent span
Physics
Primary field (CPC G)

Patents· 24 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores46%
G06FElectric digital data processing36%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
H01LSemiconductor devices2%
PatentTitleYear
10,878,878Protocol for memory power-mode control202010,672,450Protocol for memory power-mode control202010,650,872Memory component with multiple command/address sampling modes202010,622,053Protocol for memory power-mode control202010,614,869Protocol for memory power-mode control202010,431,290Protocol for memory power-mode control201910,268,619Cross-threaded memory system201910,262,718DRAM having a plurality of registers201910,170,170Memory control component with dynamic command/address signaling rate20199,886,993'Protocol for memory power-mode control'20189,818,463'Memory control component with inter-rank skew tolerance'20179,563,597'High capacity memory systems with inter-rank skew tolerance'20179,502,096'Protocol for memory power-mode control'20169,355,021'Cross-threaded memory system'20169,349,422'Supporting calibration for sub-rate operation in clocked memory systems'20169,111,645'Request-command encoding for reduced-data-rate testing'20159,036,436'Supporting calibration for sub-rate operation in clocked memory systems'20158,942,056'Protocol for memory power-mode control'20158,510,495'Cross-threaded memory system'20138,391,099'Integrated circuit memory device, system and method having interleaved row and column control'20137,940,598'Integrated circuit memory device, system and method having interleaved row and column control'20117,769,942'Cross-threaded memory system'20107,420,874'Integrated circuit memory device, system and method having interleaved row and column control'20087,136,310'Programmable output driver turn-on time for an integrated circuit memory device'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2020Patents assigned to RAMBUS INC (23)· patent assignee history
2006–2020Based in Cupertino, CA, US· patent location history
2013–2015Patents assigned to WARE FREDERICK A (3)· patent assignee history
2013Patents assigned to KASAMSETTY KISHORE (2)· patent assignee history
2015Patents assigned to BANSAL AKASH (2)· patent assignee history
2015Patents assigned to KASAMSETTY KISHORE VEN (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
RAMBUS INC232006–2020
WARE FREDERICK A32013–2015
BANSAL AKASH22015
KASAMSETTY KISHOREself22013
KASAMSETTY KISHORE VENself22015
Locations
LocationPatentsSpan
Cupertino, California, US242006–2020