Inventor
Byung-Hoon Jeong
Inventor
Hwaseong-si, KR
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores49%
G06FElectric digital data processing14%
H03KPulse technique9%
H01LSemiconductor devices4%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
B01DSeparation1%
C02FTreatment of water, waste water, sewage, or sludge1%
G01RMeasuring electric variables1%
PatentTitleYear
11,127,462Multi-chip package with reduced calibration time and ZQ calibration method thereof202111,107,512Memory device and memory system including the same202110,824,575Buffer device supporting training operations for a plurality of memory devices, and memory module and memory system each including the buffer device202010,770,149Non-volatile memory device202010,754,563Memory device for efficiently determining whether to perform re-training operation and memory system including the same202010,741,225Non-volatile memory device and storage device including the same202010,679,717Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory202010,672,436Memory device including on-die-termination circuit202010,666,249Semiconductor package202010,600,454Non-volatile memory device and storage device including the same202010,559,373Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory202010,497,412Method and circuit for self-training of a reference voltage and memory system including the same201910,482,937Memory devices and memory systems including the same201910,482,935Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory201910,438,635Apparatus and method of transmitting and receiving data, and semiconductor package including the same201910,439,632Reference voltage generator and semiconductor device including the same201910,340,022Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory201910,291,275Reception interface circuits supporting multiple communication standards and memory systems including the same201910,205,431Nonvolatile memory device, memory system including the same and method of operating the same201910,171,269Equalizer circuit and integrated circuit including the same201910,132,865Semiconductor chip, test system, and method of testing the semiconductor chip201810,014,039Method and circuit for self-training of a reference voltage and memory system including the same20188,553,486'Semiconductor memory device correcting fuse data and method of operating the same'20138,437,206'Latency circuit and semiconductor device comprising same'20138,345,501'Semiconductor memory device correcting fuse data and method of operating the same'20138,294,499'Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same'20128,230,140'Latency control circuit and method using queuing design method'20128,045,406'Latency circuit using division method related to CAS latency and semiconductor memory device'20117,979,605'Latency control circuit and method using queuing design method'20117,675,797'CAS latency circuit and semiconductor memory device including the same'20107,486,577'Repair circuit and method of repairing defects in a semiconductor memory device'20097,375,564'Time delay compensation circuit comprising delay cells having various unit time delays'20087,336,559'Delay-locked loop, integrated circuit having the same, and method of driving the same'20087,242,232'Internal signal replication device and method'20077,215,596'Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same'20077,110,316'Shared decoupling capacitance'20066,944,089'Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (37)· patent assignee history
2005Based in Kyungki-do, KR· patent location history
2006–2008Based in Suwon-si, KR· patent location history
2007–2012Based in Gyeonggi-do, KR· patent location history
2009–2021Based in Hwaseong-si, KR· patent location history
2012–2019Patents assigned to JEONG BYUNG HOON (3)· patent assignee history
2012–2013Patents assigned to JEONG BYUNG-HOON (2)· patent assignee history
2012Patents assigned to CHUNG HOE-JU (1)· patent assignee history
2012Based in Yongin-si, KR· patent location history
2019Patents assigned to CHOI YOUNG DON (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 37 | 2005–2021 |
| JEONG BYUNG HOONself | 3 | 2012–2019 |
| JEONG BYUNG-HOONself | 2 | 2012–2013 |
| CHOI YOUNG DON | 1 | 2019 |
| CHUNG HOE-JU | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hwaseong-si, KR | 28 | 2009–2021 |
| Gyeonggi-do, KR | 5 | 2007–2012 |
| Suwon-si, KR | 2 | 2006–2008 |
| Yongin-si, KR | 1 | 2012 |
| Kyungki-do, KR | 1 | 2005 |