Inventor
Charles F. Marino
Inventor
Round Rock, TX, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing57%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
H04NPictorial communication, e.g. television5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
G01RMeasuring electric variables3%
G06TImage data processing or generation, in general3%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
H03KPulse technique3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H03MCoding2%
PatentTitleYear
10,664,398Link-level cyclic redundancy check replay for non-blocking coherence flow202010,642,760Techniques for command arbitation in symmetric multiprocessor systems202010,606,777Dropped command truncation for efficient queue utilization in multiprocessor data processing system202010,552,354Managing starvation in a distributed arbitration scheme202010,394,636Techniques for managing a hang condition in a data processing system with shared memory201910,275,379Managing starvation in a distributed arbitration scheme201910,223,186Coherency error detection and reporting in a processor20199,626,229'Processor performance monitoring unit synchronization'20179,582,442'Intercomponent data communication between different processors'20179,575,921'Command rate configuration in data processing system'20179,569,394'Intercomponent data communication'20179,563,594'Intercomponent data communication between multiple time zones'20179,515,663'Dynamic prescaling for performance counters'20169,495,312'Determining command rate based on dropped commands'20169,495,314'Determining command rate based on dropped commands'20169,454,484'Integrated circuit system having decoupled logical and physical interfaces'20169,419,625'Dynamic prescaling for performance counters'20169,384,157'Intercomponent data communication'20169,367,505'Coherency overcommit'20169,367,504'Coherency overcommit'20169,342,387'Hardware-assisted interthread push communication'20169,286,148'Hardware-assisted interthread push communication'20169,286,220'Provision of early data from a lower level cache memory'20169,251,111'Command rate configuration in data processing system'20169,208,091'Coherent attached processor proxy having hybrid directory'20159,208,092'Coherent attached processor proxy having hybrid directory'20159,176,877'Provision of early data from a lower level cache memory'20159,122,608'Frequency determination across an interface of a data processing system'20159,086,975'Coherent proxy for attached processor'20159,069,674'Coherent proxy for attached processor'20159,058,273'Frequency determination across an interface of a data processing system'20158,893,126'Binding a process to a special purpose processing element having characteristics of a processor'20148,656,128'Aggregate data processing system having multiple overlapping synthetic computers'20148,429,382'Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology'20138,370,595'Aggregate data processing system having multiple overlapping synthetic computers'20137,917,730'Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller'20117,865,650'Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements'20116,999,105'Image scaling employing horizontal partitioning'20066,803,922'Pixel formatter for two-dimensional graphics engine of set-top box system'20046,784,893'Raster operation unit'20046,061,403'Computer program product for selectively reducing bandwidth of real-time video data'20005,986,714'Method, apparatus and computer program product for selectively reducing bandwidth of real-time video data'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2020Patents assigned to IBM (42)· patent assignee history
1999–2004Based in Vestal, NY, US· patent location history
2006–2020Based in Round Rock, TX, US· patent location history
2013–2014Patents assigned to GUTHRIE GUY L (3)· patent assignee history
2013–2014Patents assigned to MARINO CHARLES F (3)· patent assignee history
2013–2014Patents assigned to STARKE WILLIAM J (3)· patent assignee history
2015Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
2015Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 42 | 1999–2020 |
| GUTHRIE GUY L | 3 | 2013–2014 |
| MARINO CHARLES Fself | 3 | 2013–2014 |
| STARKE WILLIAM J | 3 | 2013–2014 |
| GLOBALFOUNDRIES INC | 2 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Round Rock, Texas, US | 37 | 2006–2020 |
| Vestal, New York, US | 4 | 1999–2004 |
| Austin, Texas, US | 1 | 2015 |