Inventor

James W. Tschanz

Inventor

Portland, OR, US

Overview

90→

Patents

2002–2021

Patent span

Physics

Primary field (CPC G)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing25%

H03KPulse technique20%

G11CStatic stores19%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

G05FSystems for regulating electric or magnetic variables6%

G01RMeasuring electric variables4%

H04LTransmission of digital information, e.g. telegraphic communication3%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%

G10LSpeech analysis techniques or speech synthesis1%

PatentTitleYear

10,984,855Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks2021 10,698,432Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators2020 10,600,462Bitcell state retention2020 10,359,834Graphics processor sub-domain voltage regulation2019 10,297,302Magnetic storage cell memory with back hop-prevention2019 10,217,509Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks2019 10,199,091Retention minimum voltage determination techniques2019 10,122,347Adaptive voltage system for aging guard-band reduction2018 10,024,916Sequential circuit with error detection2018 9,948,179Apparatus for charge recovery during low power mode2018 9,916,884'Physically unclonable function circuit using resistive memory device'2018 9,870,012'Digitally phase locked low dropout regulator apparatus and system using ring oscillators'2018 9,830,988Apparatus to reduce retention failure in complementary resistive memory2017 9,805,790'Memory cell with retention using resistive memory'2017 9,772,903'Resilient register file circuit for dynamic variation tolerance and method of operating the same'2017 9,762,241'Physically unclonable function circuit including memory elements'2017 9,720,484'Apparatus and method to reduce memory power consumption by inverting data'2017 9,722,606'Digital clamp for state retention'2017 9,680,472'Voltage level shifter circuit'2017 9,666,257'Bitcell state retention'2017 9,633,716'Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks'2017 9,633,654'Low power voice detection'2017 9,627,039'Apparatus for reducing write minimum supply voltage for memory'2017 9,621,163'Current steering level shifter'2017 9,594,625'Sequential circuit with error detection'2017 9,577,641'Spin transfer torque based memory elements for programmable device arrays'2017 9,563,263'Graphics processor sub-domain voltage regulation'2017 9,520,877'Apparatus and method for detecting or repairing minimum delay errors'2016 9,514,796'Magnetic storage cell memory with back hop-prevention'2016 9,484,917'Digital clamp for state retention'2016 9,455,011'Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current'2016 9,406,313'Adaptive microphone sampling rate techniques'2016 9,385,722'Voltage level shifter circuit'2016 9,373,395'Apparatus to reduce retention failure in complementary resistive memory'2016 9,369,277'Encryption code generation using spin-torque NANO-oscillators'2016 9,329,918'Resilient register file circuit for dynamic variation tolerance and method of operating the same'2016 9,299,395'Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks'2016 9,270,278'Spin transfer torque based memory elements for programmable device arrays'2016 9,230,636'Apparatus for dual purpose charge pump'2016 9,229,054'Self-contained, path-level aging monitor apparatus and method'2016 9,189,014'Sequential circuit with error detection'2015 9,153,304'Apparatus for reducing write minimum supply voltage for memory'2015 9,015,507'Memory data inversion for reducing power consumption'2015 8,901,819'Multi-supply sequential logic unit'2014 8,848,858'Integrated non-volatile monotonic counters'2014 8,589,706'Data inversion based approaches for reducing memory power consumption'2013 8,488,390'Circuits and methods for memory'2013 8,312,306'Component reliability budgeting system'2012 8,288,846'Power management integrated circuit'2012 7,689,845'Component reliability budgeting system'2010 7,684,520'Method and apparatus for bus repeater tapering'2010 7,653,850'Delay fault detection using latch with error sampling'2010 7,562,316'Apparatus for power consumption reduction'2009 7,444,528'Component reliability budgeting system'2008 7,423,899'SRAM device having forward body bias control'2008 7,409,631'Error-detection flip-flop'2008 7,400,186'Bidirectional body bias regulation'2008 7,397,395'Representative majority voter for bus invert coding'2008 7,376,849'Method, apparatus and system of adjusting one or more performance-related parameters of a processor'2008 7,342,845'Method and apparatus to clamp SRAM supply voltage'2008 7,326,972'Interconnect structure in integrated circuits'2008 7,307,899'Reducing power consumption in integrated circuits'2007 7,282,966'Frequency management apparatus, systems, and methods'2007 7,236,005'Majority voter circuit design'2007 7,236,045'Bias generator for body bias'2007 7,206,249'SRAM cell power reduction circuit'2007 7,190,286'Single-stage and multi-stage low power interconnect architectures'2007 7,183,795'Majority voter apparatus, systems, and methods'2007 7,164,307'Bias generator for body bias'2007 7,120,804'Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency'2006 7,109,776'Gating for dual edge-triggered clocking'2006 7,106,128'Processor apparatus with body bias circuitry to delay thermal throttling'2006 7,096,433'Method for power consumption reduction'2006 7,075,180'Method and apparatus for applying body bias to integrated circuit die'2006 7,051,295'IC design process including automated removal of body contacts from MOSFET devices'2006 7,020,041'Method and apparatus to clamp SRAM supply voltage'2006 7,015,741'Adaptive body bias for clock skew compensation'2006 6,992,603'Single-stage and multi-stage low power interconnect architectures'2006 6,970,018'Clocked cycle latch circuit'2005 6,917,237'Temperature dependent regulation of threshold voltage'2005 6,806,739'Time-borrowing N-only clocked cycle latch'2004 6,784,722'Wide-range local bias generator for body bias grid'2004 6,784,688'Skewed repeater bus'2004 6,763,484'Body bias using scan chains'2004 6,744,301'System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise'2004 6,642,765'Transmission-gate based flip-flop'2003 6,632,686'Silicon on insulator device design having improved floating body effect'2003 6,608,513'Flip-flop circuit having dual-edge triggered pulse generator'2003 6,515,513'Reducing leakage currents in integrated circuits'2003 6,429,711'Stack-based impulse flip-flop with stack node pre-charge and stack node pre-discharge'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2021Patents assigned to INTEL CORP (89)· patent assignee history

2002–2010Based in Hillsboro, OR, US· patent location history

2004–2021Based in Portland, OR, US· patent location history

2012–2017Patents assigned to TSCHANZ JAMES W (13)· patent assignee history

2012–2016Patents assigned to DE VIVEK K (9)· patent assignee history

2013–2016Patents assigned to KULKARNI JAYDEEP P (6)· patent assignee history

2014–2017Patents assigned to RAYCHOWDHURY ARIJIT (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	89	2002–2021
TSCHANZ JAMES Wself	13	2012–2017
DE VIVEK K	9	2012–2016
KULKARNI JAYDEEP P	6	2013–2016
RAYCHOWDHURY ARIJIT	5	2014–2017

Locations

Location	Patents	Span
Portland, OR, US	82	2004–2021
Hillsboro, OR, US	8	2002–2010