Inventor

Praneet Adusumilli

Inventor

Albany, NY, US

Overview

2013–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 120 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices30%

H10DInorganic electric semiconductor devices24%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H10BElectronic memory devices4%

H10NElectric solid-state devices not otherwise provided for2%

G11CStatic stores1%

H10HInorganic light-emitting semiconductor devices having potential barriers1%

G06FElectric digital data processing0%

G06NComputing arrangements based on specific computational models0%

PatentTitleYear

11,068,971Method, medium, and system for virtual try-on coordination via communications sessions2021 11,050,023CBRAM with controlled bridge location2021 11,038,097Magnetic structures with tapered edges2021 11,011,697Faceted sidewall magnetic tunnel junction structure2021 10,943,988Thermally stable salicide formation for salicide first contacts2021 10,937,889Forming thermally stable salicide for salicide first contacts2021 10,916,471Dual silicide liner flow for enabling low contact resistance2021 10,915,811Intercalation cells for multi-task learning2021 10,903,424Resistive RAM cell structure for gradual set programming2021 10,885,979Paired intercalation cells for drift migration2021 10,825,740Low resistance source-drain contacts using high temperature silicides2020 10,784,194BEOL embedded high density vertical resistor structure2020 10,756,163Conformal capacitor structure formed by a single process2020 10,741,492FinFET fuses formed at tight pitch dimensions2020 10,734,575ReRAM structure formed by a single process2020 10,727,070Liner-less contact metallization2020 10,699,949Mechanically stable cobalt contacts2020 10,692,722Single process for linear and metal fill2020 10,685,888Low resistance source-drain contacts using high temperature silicides2020 10,665,541Biconvex low resistance metal wire2020 10,651,042Salicide bottom contacts2020 10,600,860Precise/designable FinFET resistor structure2020 10,593,659Deep high capacity capacitor for bulk substrates2020 10,580,966Faceted sidewall magnetic tunnel junction structure2020 10,573,567Sacrificial cap for forming semiconductor contact2020 10,573,596FinFET fuses formed at tight pitch dimensions2020 10,546,915Buried MIM capacitor structure with landing pads2020 10,546,941Forming thermally stable salicide for salicide first contacts2020 10,546,776Dual silicide liner flow for enabling low contact resistance2020 10,546,918Multilayer buried metal-insultor-metal capacitor structures2020 10,541,207Biconvex low resistance metal wire2020 10,541,202Programmable buried antifuse2020 10,510,829Secondary use of aspect ratio trapping trenches as resistor structures2019 10,461,148Multilayer buried metal-insultor-metal capacitor structures2019 10,453,935Thermally stable salicide formation for salicide first contacts2019 10,446,746ReRAM structure formed by a single process2019 10,431,542Low resistance seed enhancement spacers for voidless interconnect structures2019 10,431,503Sacrificial cap for forming semiconductor contact2019 10,410,966BEOL embedded high density vertical resistor structure2019 10,396,165Thin low defect relaxed silicon germanium layers on bulk silicon substrates2019 10,388,600Binary metallization structure for nanoscale dual damascene interconnects2019 10,388,721Conformal capacitor structure formed by a single process2019 10,361,277Low resistivity wrap-around contacts2019 10,355,094Low resistance contact structures for trench structures2019 10,340,355Method of forming a dual metal interconnect structure2019 10,340,221Stacked FinFET anti-fuse2019 10,312,097Salicide bottom contacts2019 10,304,773Low resistance contact structures including a copper fill for trench structures2019 10,304,735Mechanically stable cobalt contacts2019 10,304,938Maskless method to reduce source-drain contact resistance in CMOS devices2019 10,304,841Metal FinFET anti-fuse2019 10,269,698Binary metallization structure for nanoscale dual damascene interconnects2019 10,269,710Multi-level metallization interconnect structure2019 10,249,724Low resistance contact structures for trench structures2019 10,249,501Single process for liner and metal fill2019 10,224,281Metallic blocking layer for reliable interconnects and contacts2019 10,211,095High performance middle of line interconnects2019 10,211,207Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices2019 10,170,360Reflow enhancement layer for metallization structures2019 10,170,423Metal cap integration by local alloying2019 10,170,419Biconvex low resistance metal wire2019 10,147,680Method to reduce variability in contact resistance2018 10,141,308Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices2018 10,128,188High aspect ratio contact metallization without seams2018 10,128,151Devices and methods of cobalt fill metallization2018 10,121,789Self-aligned source/drain contacts2018 10,115,665Semiconductor resistor structures embedded in a middle-of-the-line (MOL) dielectric2018 10,109,740Programmable bulk FinFET antifuses2018 10,090,151Structure and method to reduce copper loss during metal cap formation2018 10,090,287Deep high capacity capacitor for bulk substrates2018 10,074,727Low resistivity wrap-around contacts2018 10,056,329Programmable buried antifuse2018 10,056,391Vertically stacked FinFET fuse2018 10,049,980Low resistance seed enhancement spacers for voidless interconnect structures2018 10,038,050FinFET resistor and method to fabricate same2018 10,037,942Low resistance contact structures for trench structures2018 10,032,721Low resistance contact structures for trench structures2018 10,026,693Method, apparatus, and system for MOL interconnects without titanium liner2018 10,008,507Metal FinFET anti-fuse2018 10,008,563Dielectric with air gaps for use in semiconductor devices2018 10,002,789High performance middle of line interconnects2018 9,997,453Antifuse having comb-like top electrode2018 9,997,590FinFET resistor and method to fabricate same2018 9,997,416Low resistance dual liner contacts for fin field-effect transistors (FinFETs)2018 9,978,750Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices2018 9,960,240Low resistance contact structures for trench structures2018 9,954,050Precise/designable FinFET resistor structure2018 9,947,621Structure and method to reduce copper loss during metal cap formation2018 9,941,204III-V compatible anti-fuses2018 9,935,051Multi-level metallization interconnect structure2018 9,934,977Salicide bottom contacts2018 9,922,941'Thin low defect relaxed silicon germanium layers on bulk silicon substrates'2018 9,881,798'Metal cap integration by local alloying'2018 9,876,075Method of forming dielectric with air gaps for use in semiconductor devices2018 9,865,538'Metallic blocking layer for reliable interconnects and contacts'2018 9,859,219'Copper wiring structures with copper titanium encapsulation'2018 9,859,403'Multiple step thin film deposition method for high conformality'2018 9,852,981III-V compatible anti-fuses2017 9,842,770'Reflow enhancement layer for metallization structures'2017 9,837,357Method to reduce variability in contact resistance2017 9,831,254Multiple breakdown point low resistance anti-fuse structure2017 9,824,967'Semiconductor resistor structures embedded in a middle-of-the-line (MOL) dielectric'2017 9,812,522'Metal-insulator-metal capacitor fabrication with unitary sputtering process'2017 9,805,973'Dual silicide liner flow for enabling low contact resistance'2017 9,805,989'Sacrificial cap for forming semiconductor contact'2017 9,786,596'Fuse formed from III-V aspect ratio structure'2017 9,786,595'Antifuse having comb-like top electrode'2017 9,768,077'Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)'2017 9,741,812'Dual metal interconnect structure'2017 9,735,165'Vertically stacked FinFET fuse'2017 9,722,038'Metal cap protection layer for gate and contact metallization'2017 9,679,807'Method, apparatus, and system for MOL interconnects without titanium liner'2017 9,613,899'Epitaxial semiconductor fuse for FinFET structure'2017 9,576,957'Self-aligned source/drain contacts'2017 9,570,574'Recessed metal liner contact with copper fill'2017 9,564,310'Metal-insulator-metal capacitor fabrication with unitary sputtering process'2017 9,496,225'Recessed metal liner contact with copper fill'2016 9,437,714'Selective gate contact fill metallization'2016 8,999,799'Maskless dual silicide contact formation'2015 8,415,677'Field-effect transistor device having a metal gate stack with an oxygen barrier layer'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2021Patents assigned to IBM (113)· patent assignee history

2013Patents assigned to ADUSUMILLI PRANEET (1)· patent assignee history

2013Patents assigned to CALLEGARI ALESSANDRO (1)· patent assignee history

2013Based in Evanston, IL, US· patent location history

2015–2021Based in Albany, NY, US· patent location history

2017–2020Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history

2019–2021Based in Somerset, NJ, US· patent location history

2020–2021Patents assigned to ELPIS TECH INC (2)· patent assignee history

2021Based in Plano, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	113	2013–2021
GLOBALFOUNDRIES INC	6	2017–2020
ELPIS TECH INC	2	2020–2021
ADUSUMILLI PRANEETself	1	2013
CALLEGARI ALESSANDRO	1	2013

Locations

Location	Patents	Span
Albany, New York, US	93	2015–2021
Somerset, New Jersey, US	25	2019–2021
Plano, Texas, US	1	2021
Evanston, Illinois, US	1	2013