Inventor
Hiroyuki Akatsu
Inventor
Yorktown Heights, NY, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10DInorganic electric semiconductor devices15%
H10BElectronic memory devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
A61BDiagnosis6%
LOC146%
A61GTransport, personal conveyances, or accommodation specially adapted for patients or disabled persons5%
B08BCleaning in general3%
G01GWeighing3%
PatentTitleYear
10,888,279Biometric information monitoring system202110,758,187Respiration waveform drawing system and biological information monitoring system202010,617,326Respiration waveform drawing system202010,610,430Respiration waveform drawing system and respiration waveform drawing method202010,390,735Body state detecting apparatus, body state detecting method and bed system2019D0817973Display screen with graphical user interface2018D0817974Display screen with graphical user interface2018D0806719'Display screen with graphical user interface'2018D0804497'Display screen with graphical user interface'2017D0804498'Display screen with graphical user interface'20179,043,006'Acoustic characteristics setting support system and acoustic characteristics setting apparatus'20158,655,696'System for performing schedule management, schedule management method and program'20148,396,823'Automatic designing system, automatic designing method and automatic designing program for automatically designing architecture for system components'20137,974,866'System and method for managing workflow among a plurality of business processes associated respectively with users having access rights to artifacts'20117,615,457'Method of fabricating self-aligned bipolar transistor having tapered collector'20097,601,646'Top-oxide-early process and array top oxide planarization'20097,462,547'Method of fabricating a bipolar transistor having reduced collector-base capacitance'20087,425,754'Structure and method of self-aligned bipolar transistor having tapered collector'20087,190,046'Bipolar transistor having reduced collector-base capacitance'20076,967,136'Method and structure for improved trench processing'20056,957,589'Temperature compensator of torque sensor'20056,893,938'STI formation for vertical and planar transistors'20056,887,761'Vertical semiconductor devices'20056,849,153'Removal of post-rie polymer on A1/CU metal line'20056,809,027'Self-aligned borderless contacts'20046,806,138'Integration scheme for enhancing capacitance of trench capacitors'20046,806,177'Method of making self-aligned borderless contacts'20046,724,031'Method for preventing strap-to-strap punch through in vertical DRAMs'20046,723,611'Vertical hard mask'20046,485,894'Method to self-align a lithographic pattern to a workpiece'20026,449,202'DRAM direct sensing scheme'20026,387,782'Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer'20026,379,577'Hydrogen peroxide and acid etchant for a wet etch process'20026,333,274'Method of manufacturing a semiconductor device including a seamless shallow trench isolation step'20016,329,271'Self-aligned channel implantation'20016,329,704'Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer'20016,319,794'Structure and method for producing low leakage isolation devices'20016,297,530'Self aligned channel implantation'20016,281,084'Disposable spacers for improved array gapfill in high density DRAMs'20016,060,388'Conductors for microelectronic circuits and method of manufacture'20006,039,055'Wafer cleaning with dissolved gas concentration control'20006,021,789'Wafer cleaning system with progressive megasonic wave'20005,980,770'Removal of post-RIE polymer on Al/Cu metal line'19995,934,299'Apparatus and method for improved washing and drying of semiconductor wafers'19995,932,493'Method to minimize watermarks on silicon substrates'19995,807,439'Apparatus and method for improved washing and drying of semiconductor wafers'19985,717,635'High density EEPROM for solid state file'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2014Patents assigned to IBM (34)· patent assignee history
1998–2005Patents assigned to SIEMENS AG (4)· patent assignee history
1998–2009Based in Yorktown Heights, NY, US· patent location history
2001–2005Patents assigned to INFINEON TECHNOLOGIES CORP (5)· patent assignee history
2011–2021Based in Tokyo, JP· patent location history
2015Based in Fukushima, JP· patent location history
2017–2018Patents assigned to MINEBEA CO LTD (3)· patent assignee history
2017–2018Based in Nagano, JP· patent location history
2018–2021Patents assigned to MINEBEA MITSUMI INC (8)· patent assignee history
2020Based in Minato-ku, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 34 | 1998–2014 |
| MINEBEA MITSUMI INC | 8 | 2018–2021 |
| INFINEON TECHNOLOGIES CORP | 5 | 2001–2005 |
| SIEMENS AG | 4 | 1998–2005 |
| MINEBEA CO LTD | 3 | 2017–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yorktown Heights, New York, US | 30 | 1998–2009 |
| Tokyo, JP | 8 | 2011–2021 |
| Minato-ku, JP | 3 | 2020 |
| Nagano, JP | 2 | 2017–2018 |
| Fukushima, JP | 1 | 2015 |