Inventor
Ritu Shrivastava
Inventor
Fremont, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices31%
G11CStatic stores15%
H10DInorganic electric semiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
B82YSpecific uses or applications of nanostructures6%
H10KOrganic electric solid-state devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G05BControl or regulating systems in general2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G07CTime or attendance registers2%
PatentTitleYear
11,080,649Remote access monitoring20218,395,926'Memory cell with resistance-switching layers and lateral arrangement'20137,799,598'Processing systems and methods for molecular memory'20107,642,546'Molecular memory devices including solid-state dielectric layers and related methods'20107,358,113'Processing systems and methods for molecular memory'20086,921,688'Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrate'20056,903,434'Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate'20056,589,834'Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current'20036,472,267'DRAM cell having storage capacitor contact self-aligned to bit lines and word lines'20026,429,076'Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereof'20026,392,267'Flash EPROM array with self-aligned source contacts and programmable sector erase architecture'20026,373,089'DRAM cell having storage capacitor contact self-aligned to bit lines and word lines'20026,258,714'Self-aligned contacts for salicided MOS devices'20016,166,409'Flash EPROM memory cell having increased capacitive coupling'20006,133,602'Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures'20006,020,237'Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures'20005,994,730'DRAM cell having storage capacitor contact self-aligned to bit lines and word lines'19995,856,944'Self-converging over-erase repair method for flash EPROM'19995,731,606'Reliable edge cell array design'19985,701,264'Dynamic random access memory cell having increased capacitance'19975,672,535'Method of fabricating DRAM cell with self-aligned contact'19975,557,122'Semiconductor electrode having improved grain structure and oxide growth properties'19965,518,942'Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant'19965,416,738'Single transistor flash EPROM cell and method of operation'19954,764,248'Rapid thermal nitridized oxide locos process'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2013Based in Fremont, CA, US· patent location history
1995–2003Patents assigned to ALLIANCE SEMICONDUCTOR CORP (15)· patent assignee history
1996Patents assigned to ALLIANCE SEMICONDUCTORS CORP (1)· patent assignee history
2005Patents assigned to ALLIANCE SEMICONDUCTOR (1)· patent assignee history
2005Patents assigned to ALLIANCE SEMICONDUCTORS (1)· patent assignee history
2008–2010Patents assigned to ZETTACORE INC (3)· patent assignee history
2021Based in Saratoga, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALLIANCE SEMICONDUCTOR CORP | 15 | 1995–2003 |
| ZETTACORE INC | 3 | 2008–2010 |
| ALLIANCE SEMICONDUCTOR | 1 | 2005 |
| ALLIANCE SEMICONDUCTORS | 1 | 2005 |
| ALLIANCE SEMICONDUCTORS CORP | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 24 | 1988–2013 |
| Saratoga, California, US | 1 | 2021 |