LexDanaLexDanabeta
Inventor

Kuen-Ting Shiu

Inventor
White Plains, NY, US

Overview

104→
Patents
2008–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 104 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices24%
H10DInorganic electric semiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10HInorganic light-emitting semiconductor devices having potential barriers4%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution4%
G02BOptical elements, systems or apparatus3%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
10,998,420Direct growth of lateral III-V bipolar transistor on silicon substrate202110,756,506III-V photonic integrated circuits on silicon substrate202010,686,090Wafer bonded solar cells and fabrication methods202010,601,199Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same202010,460,948Stress assisted wet and dry epitaxial lift off201910,439,356III-V photonic integrated circuits on silicon substrate201910,256,608Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201910,217,632Integration of III-V compound materials on silicon201910,141,719Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201810,135,226Resonant cavity strained Group III-V photodetector and LED on silicon substrate and method to fabricate same201810,122,153Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201810,043,663Enhanced defect reduction for heteroepitaxy by seed shape engineering201810,014,377III-V field effect transistor on a dielectric layer20189,984,873Preparation of low defect density of III-V on Si for device fabrication20189,966,735III-V lasers with integrated silicon photonic circuits20189,887,264'Nanowire field effect transistor (FET) and method for fabricating the same'20189,882,021'Planar III-V field effect transistor (FET) on dielectric layer'20189,864,135'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material'20189,865,469'Epitaxial lift-off process with guided etching'20189,865,769'Back contact LED through spalling'20189,818,901'Wafer bonded solar cells and fabrication methods'20179,726,819'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth'20179,704,958'III-V field effect transistor on a dielectric layer'20179,660,116'Nanowires formed by employing solder nanodots'20179,653,308'Epitaxial lift-off process with guided etching'20179,608,160'Polarization free gallium nitride-based photonic devices on nanopatterned silicon'20179,595,805'III-V photonic integrated circuits on silicon substrate'20179,590,393'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth'20179,589,791'Compound finFET device including oxidized III-V fin isolator'20179,570,296'Preparation of low defect density of III-V on Si for device fabrication'20179,564,494'Enhanced defect reduction for heteroepitaxy by seed shape engineering'20179,548,355'Compound finFET device including oxidized III-V fin isolator'20179,508,640'Multiple via structure and method'20169,496,347'Graded buffer epitaxy in aspect ratio trapping'20169,459,797'Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells'20169,431,301'Nanowire field effect transistor (FET) and method for fabricating the same'20169,412,744'III-V CMOS integration on silicon substrate via embedded germanium-containing layer'20169,406,530'Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping'20169,407,066'III-V lasers with integrated silicon photonic circuits'20169,406,566'Integration of III-V compound materials on silicon'20169,401,583'Laser structure on silicon using aspect ratio trapping growth'20169,397,226'Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts'20169,395,489'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material'20169,391,144'Selective gallium nitride regrowth on (100) silicon'20169,368,407'Crack control for substrate separation'20169,344,200'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth'20169,337,281'Planar semiconductor growth on III-V material'20169,324,853'III-V semiconductor device having self-aligned contacts'20169,318,641'Nanowires formed by employing solder nanodots'20169,287,115'Planar III-V field effect transistor (FET) on dielectric layer'20169,287,362'Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts'20169,263,626'Crystalline thin film photovoltaic cell'20169,236,251'Heterogeneous integration of group III nitride on silicon for advanced integrated circuits'20169,231,133'Nanowires formed by employing solder nanodots'20169,159,822'III-V semiconductor device having self-aligned contacts'20159,123,569'Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator'20159,105,571'Interface engineering to optimize metal-III-V contacts'20159,099,381'Selective gallium nitride regrowth on (100) silicon'20159,093,532'Overlapped III-V finFET with doped semiconductor extensions'20159,087,775'Planar semiconductor growth on III-V material'20159,087,905'Transistor formation using cold welding'20159,082,690'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20159,082,689'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20159,070,617'Reduced S/D contact resistance of III-V mosfet using low temperature metal-induced crystallization of n+ Ge'20159,059,231'T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator'20159,059,073'Method for controlled removal of a semiconductor device layer from a base substrate'20159,059,232'T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator'20159,059,288'Overlapped III-V finfet with doped semiconductor extensions'20159,059,075'Selective gallium nitride regrowth on (100) silicon'20159,059,272'Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation'20159,059,271'Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation'20159,053,930'Heterogeneous integration of group III nitride on silicon for advanced integrated circuits'20159,048,173'Dual phase gallium nitride material formation on (100) silicon'20159,040,392'Method for controlled removal of a semiconductor device layer from a base substrate'20158,975,635'Co-integration of elemental semiconductor devices and compound semiconductor devices'20158,946,054'Crack control for substrate separation'20158,941,147'Transistor formation using cold welding'20158,937,299'III-V finFETs on silicon substrate'20158,927,398'Group III nitrides on nanopatterned substrates'20158,927,319'Methods of preparing flexible photovoltaic devices using epitaxial liftoff, and preserving the integrity of growth substrates used in epitaxial growth'20158,907,381'Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer'20148,889,541'Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer'20148,841,177'Co-integration of elemental semiconductor devices and compound semiconductor devices'20148,835,266'Method and structure for compound semiconductor contact'20148,828,824'III-V field effect transistory (FET) and III-V semiconductor on insulator (IIIVOI) FET, integrated circuit (IC) chip and method of manufacture'20148,822,317'Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact'20148,809,860'III-V compound semiconductor material passivation with crystalline interlayer'20148,796,120'High throughput epitaxial lift off for flexible electronics'20148,772,116'Dielectric equivalent thickness and capacitance scaling for semiconductor devices'20148,628,996'Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells'20148,610,172'FETs with hybrid channel materials'20138,604,519'Self-aligned III-V field effect transistor (FET) and integrated circuit (IC) chip'20138,598,665'Controlling threshold voltage in carbon based field effect transistors'20138,541,315'High throughput epitaxial lift off for flexible electronics'20138,536,043'Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge'20138,524,614'III-V compound semiconductor material passivation with crystalline interlayer'20138,492,187'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20138,482,033'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20138,466,493'Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture'20138,420,474'Controlling threshold voltage in carbon based field effect transistors'20138,378,385'Methods of preparing flexible photovoltaic devices using epitaxial liftoff, and preserving the integrity of growth substrates used in epitaxial growth'20137,915,521'Type II quantum dot solar cells'20117,826,693'Monolithically integrated reconfigurable optical add-drop multiplexer'20107,343,061'Integrated photonic amplifier and detector'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008Based in Princeton, NJ, US· patent location history
2010–2015Based in Ann Arbor, MI, US· patent location history
2013–2021Patents assigned to IBM (91)· patent assignee history
2013–2017Patents assigned to SHIU KUEN-TING (20)· patent assignee history
2013–2017Patents assigned to CHENG CHENG-WEI (10)· patent assignee history
2013–2020Based in White Plains, NY, US· patent location history
2014–2017Patents assigned to SADANA DEVENDRA K (7)· patent assignee history
2015–2021Based in Yorktown Heights, NY, US· patent location history
2016–2018Patents assigned to GLOBALFOUNDRIES INC (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM912013–2021
SHIU KUEN-TINGself202013–2017
CHENG CHENG-WEI102013–2017
GLOBALFOUNDRIES INC82016–2018
SADANA DEVENDRA K72014–2017
Locations
LocationPatentsSpan
White Plains, New York, US572013–2020
Yorktown Heights, New York, US432015–2021
Ann Arbor, MI, US32010–2015
Princeton, New Jersey, US12008