Inventor
Bechara F. Boury
Inventor
Boca Raton, FL, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing90%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
9,201,801'Computing device with asynchronous auxiliary execution unit'20155,966,728'Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device'19995,835,738'Address space architecture for multiple bus computer systems'19985,673,414'Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device'19975,644,729'Bidirectional data buffer for a bus-to-bus interface unit in a computer system'19975,621,897'Method and apparatus for arbitrating for a bus to enable split transaction bus protocols'19975,619,729'Power management of DMA slaves with DMA traps'19975,548,786'Dynamic bus sizing of DMA transfers'19965,544,346'System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus'19965,499,346'Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus'19965,450,551'System direct memory access (DMA) support logic for PCI based computer system'19955,396,602'Arbitration logic for multiple bus computer system'19955,381,538'DMA controller including a FIFO register and a residual register for data buffering and having different operating modes'19955,333,274'Error detection and recovery in a DMA controller'19945,313,627'Parity error detection and recovery'19945,301,282'Controlling bus allocation using arbitration hold'19945,265,211'Arbitration control logic for computer system having dual bus architecture'19935,239,631'CPU bus allocation control'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2015Patents assigned to IBM (18)· patent assignee history
1993–1998Based in Boca Raton, FL, US· patent location history
1997Patents assigned to INTEL CORP (1)· patent assignee history
1997Based in Milpitas, CA, US· patent location history
1999–2015Based in Raleigh, NC, US· patent location history
2015Patents assigned to BOURY BECHARA F (1)· patent assignee history
2015Patents assigned to MITCHELL MICHAEL BRYAN (1)· patent assignee history
2015Patents assigned to STEINMETZ PAUL MICHAEL (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 1993–2015 |
| BOURY BECHARA Fself | 1 | 2015 |
| INTEL CORP | 1 | 1997 |
| MITCHELL MICHAEL BRYAN | 1 | 2015 |
| STEINMETZ PAUL MICHAEL | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boca Raton, Florida, US | 15 | 1993–1998 |
| Raleigh, NC, US | 2 | 1999–2015 |
| Milpitas, California, US | 1 | 1997 |