LexDanaLexDanabeta
Inventor

Isik C. Kizilyalli

Inventor
San Francisco, CA, US

Overview

131→
Patents
1997–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 131 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation6%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
C23CCoating metallic material1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
H01JElectric discharge tubes or discharge lamps1%
PatentTitleYear
11,121,272Self-bypass diode function for gallium arsenide photovoltaic devices202110,916,676Optoelectronic devices including heterojunction and intermediate layer202110,854,727High power gallium nitride electronics using miscut substrates202010,797,187Photovoltaic device with back side contacts202010,566,439High power gallium nitride electronics using miscut substrates202010,347,736High power gallium nitride electronics using miscut substrates20199,954,131Optoelectronic devices including heterojunction and intermediate layer20189,716,196'Self-bypass diode function for gallium arsenide photovoltaic devices'20179,691,921'Textured metallic back reflector'20179,525,039'Method of fabricating a merged P-N junction and schottky diode with regrown gallium nitride layer'20169,508,838'InGaN ohmic source contacts for vertical power devices'20169,502,544'Method and system for planar regrowth in GaN electronic devices'20169,484,470'Method of fabricating a GaN P-i-N diode using implantation'20169,472,684'Lateral GaN JFET with vertical drift region'20169,450,112'GaN-based Schottky barrier diode with algan surface layer'20169,397,186'Method of fabricating a gallium nitride merged P-I-N schottky (MPS) diode by regrowth and etch back'20169,368,582'High power gallium nitride electronics using miscut substrates'20169,330,918'Edge termination by ion implantation in gallium nitride'20169,324,844'Method and system for a GaN vertical JFET utilizing a regrown channel'20169,318,331'Method and system for diffusion and implantation in gallium nitride based devices'20169,318,619'Vertical gallium nitride JFET with gate and source electrodes on regrown gate'20169,287,389'Method and system for doping control in gallium nitride based devices'20169,269,793'Method and system for a gallium nitride self-aligned vertical MESFET'20169,224,828'Method and system for floating guard rings in gallium nitride materials'20159,196,679'Schottky diode with buried layer in GaN materials'20159,184,305'Method and system for a GAN vertical JFET utilizing a regrown gate'20159,178,099'Methods for forming optoelectronic devices including heterojunction'20159,171,923'Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode'20159,171,900'Method of fabricating a gallium nitride P-i-N diode using implantation'20159,171,751'Method and system for fabricating floating guard rings in GaN materials'20159,171,937'Monolithically integrated vertical JFET and Schottky diode'20159,159,799'Method of fabricating a merged P-N junction and schottky diode with regrown gallium nitride layer'20159,159,784'Aluminum gallium nitride etch stop layer for gallium nitride based devices'20159,136,116'Method and system for formation of P-N junctions in gallium nitride based electronics'20159,136,418'Optoelectronic devices including heterojunction and intermediate layer'20159,136,417'Methods for forming optoelectronic devices including heterojunction'20159,123,799'Gallium nitride field effect transistor with buried field plate protected lateral channel'20159,117,850'Method and system for a gallium nitride vertical JFET with self-aligned source and gate'20159,117,839'Method and system for planar regrowth in GAN electronic devices'20159,093,284'Aluminum gallium nitride etch stop layer for gallium nitride based devices'20159,093,591'Optoelectronic devices including heterojunction and intermediate layer'20159,093,395'Method and system for local control of defect density in gallium nitride based electronics'20159,082,919'Methods for forming optoelectronic devices including heterojunction'20159,059,199'Method and system for a gallium nitride vertical transistor'20159,048,366'Methods for forming optoelectronic devices including heterojunction'20159,029,680'Integration of a photovoltaic device'20159,029,210'GaN vertical superjunction device structures and fabrication methods'20159,029,687'Photovoltaic device with back side contacts'20159,006,800'Ingan ohmic source contacts for vertical power devices'20158,981,432'Method and system for gallium nitride electronic devices using engineered substrates'20158,969,180'Method and system for junction termination in GaN materials using conductivity modulation'20158,969,912'Method and system for a GaN vertical JFET utilizing a regrown channel'20158,969,994'Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode by regrowth and etch back'20158,946,725'Vertical gallium nitride JFET with gate and source electrodes on regrown gate'20158,946,788'Method and system for doping control in gallium nitride based devices'20158,941,117'Monolithically integrated vertical JFET and Schottky diode'20158,937,244'Photovoltaic device'20158,933,532'Schottky diode with buried layer in GaN materials'20158,927,999'Edge termination by ion implantation in GaN'20158,912,432'Photovoltaic device including an intermediate layer'20148,895,845'Photovoltaic device'20148,895,846'Photovoltaic device'20148,895,847'Photovoltaic device with increased light trapping'20148,866,147'Method and system for a GaN self-aligned vertical MESFET'20148,853,063'Method and system for carbon doping control in gallium nitride based devices'20148,846,482'Method and system for diffusion and implantation in gallium nitride based devices'20148,836,071'Gallium nitride-based schottky barrier diode with aluminum gallium nitride surface layer'20148,829,574'Method and system for a GaN vertical JFET with self-aligned source and gate'20148,822,311'Method of fabricating a GaN P-i-N diode using implantation'20148,823,140'GaN vertical bipolar transistor'20148,785,975'GAN vertical superjunction device structures and fabrication methods'20148,778,788'Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode'20148,749,015'Method and system for fabricating floating guard rings in GaN materials'20148,741,707'Method and system for fabricating edge termination structures in GaN materials'20148,716,716'Method and system for junction termination in GaN materials using conductivity modulation'20148,698,164'Vertical GaN JFET with gate source electrodes on regrown gate'20148,686,284'Photovoltaic device with increased light trapping'20148,674,214'Thin absorber layer of a photovoltaic device'20148,669,467'Thin absorber layer of a photovoltaic device'20148,643,134'GaN-based Schottky barrier diode with field plate'20148,592,938'GaN-based Schottky barrier diode with field plate'20138,592,298'Fabrication of floating guard rings using selective regrowth'20138,569,153'Method and system for carbon doping control in gallium nitride based devices'20138,558,242'Vertical GaN-based metal insulator semiconductor FET'20138,502,234'Monolithically integrated vertical JFET and Schottky diode'20138,358,005'Packaged gallium nitride material transistors and methods associated with the same'20138,026,596'Thermal designs of packaged gallium nitride material devices and methods of packaging'20117,820,517'Control of hot carrier injection in a metal-oxide semiconductor device'20107,605,064'Selective laser annealing of semiconductor material'20097,494,888'Device and method using isotopically enriched silicon'20097,279,744'Control of hot carrier injection in a metal-oxide semiconductor device'20077,262,476'Semiconductor device having improved power density'20076,977,128'Multi-layered semiconductor structure'20056,730,600'Method of dry etching a semiconductor device in the absence of a plasma'20046,706,609'Method of forming an alignment feature in or on a multi-layered semiconductor structure'20046,627,963'Method for fabricating a merged integrated circuit device'20036,602,758'Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing'20036,593,195'Stable memory device that utilizes ion positioning to control state of the memory device'20036,579,775'Semiconductor device having a metal gate with a work function compatible with a semiconductor device'20036,576,529'Method of forming an alignment feature in or on a multilayered semiconductor structure'20036,573,149'Semiconductor device having a metal gate with a work function compatible with a semiconductor device'20036,569,690'Monitoring system for determining progress in a fabrication activity'20036,548,854'Compound, high-K, gate and capacitor insulator layer'20036,537,867'High speed low voltage semiconductor devices and method of fabrication'20036,440,816'Alignment mark fabrication process to limit accumulation of errors in level to level overlay'20026,383,879'Semiconductor device having a metal gate with a work function compatible with a semiconductor device'20026,380,606'Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same'20026,365,511'Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability'20026,359,339'Multi-layered metal silicide resistor for Si Ic\'s'20026,339,246'Tungsten silicide nitride as an electrode for tantalum pentoxide devices'20026,335,557'Metal silicide as a barrier for MOM capacitors in CMOS technologies'20026,331,460'Method of fabricating a mom capacitor having a metal silicide barrier'20016,320,238'Gate structure for integrated circuit fabrication'20016,309,938'Deuterated bipolar transistor and method of manufacture thereof'20016,303,940'Charge injection transistor using high-k dielectric barrier layer'20016,281,138'System and method for forming a uniform thin gate oxide layer'20016,281,110'Method for making an integrated circuit including deutrium annealing of metal interconnect layers'20016,252,270'Increased cycle specification for floating-gate and method of manufacture thereof'20016,214,675'Method for fabricating a merged integrated circuit device'20016,174,807'Method of controlling gate dopant penetration and diffusion in a semiconductor device'20016,090,686'Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same'20006,087,683'Silicon germanium heterostructure bipolar transistor with indium doped base'20006,025,280'Use of SiD.sub.4 for deposition of ultra thin and controllable oxides'20006,023,093'Deuterated direlectric and polysilicon film-based semiconductor devices and method of manufacture thereof'20006,008,091'Floating gate avalanche injection MOS transistors with high K dielectric control gates'19995,994,221'Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects'19995,982,020'Deuterated bipolar transistor and method of manufacture thereof'19995,821,147'Integrated circuit fabrication'19985,767,557'PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefrom'19985,710,055'Method of making PMOSFETs having indium or gallium doped buried channels and n+ polysilicon gates and CMOS devices fabricated therefrom'19985,681,763'Method for making bipolar transistors having indium doped base'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2003Based in Orlando, FL, US· patent location history
2002–2009Based in Millburn, NJ, US· patent location history
2007–2010Based in Allentown, PA, US· patent location history
2011–2013Based in Raleigh, NC, US· patent location history
2013–2016Patents assigned to AVOGY INC (59)· patent assignee history
2013–2017Patents assigned to KIZILYALLI ISIK C (43)· patent assignee history
2013–2017Patents assigned to NIE HUI (31)· patent assignee history
2013–2015Patents assigned to BROWN RICHARD J (23)· patent assignee history
2013–2015Patents assigned to ROMANO LINDA (22)· patent assignee history
2013–2021Based in San Francisco, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AVOGY INC592013–2016
KIZILYALLI ISIK Cself432013–2017
NIE HUI312013–2017
BROWN RICHARD J232013–2015
ROMANO LINDA222013–2015
Locations
LocationPatentsSpan
San Francisco, California, US852013–2021
Orlando, Florida, US271997–2003
Millburn, New Jersey, US112002–2009
Allentown, Pennsylvania, US42007–2010
Raleigh, NC, US22011–2013