Inventor

Tony M. Brewer

Inventor

Plano, TX, US

Overview

1989–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing36%

H04LTransmission of digital information, e.g. telegraphic communication12%

G11CStatic stores7%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%

H01LSemiconductor devices7%

H10DInorganic electric semiconductor devices7%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

H04QSelecting5%

H10BElectronic memory devices4%

H04JMultiplex communication3%

PatentTitleYear

11,132,233Thread priority management in a multi-threaded, self-scheduling processor2021 11,126,587Event messaging in a system having a self-scheduling processor and a hybrid threading fabric2021 11,119,782Thread commencement using a work descriptor packet in a self-scheduling processor2021 11,119,972Multi-threaded, self-scheduling processor2021 11,119,768Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric2021 11,114,416Power and temperature management for functional blocks implemented by a 3D stacked integrated circuit2021 11,106,592Microprocessor architecture having alternative memory access paths2021 11,093,251System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network2021 11,074,078Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion2021 11,068,305System call management in a user-mode, multi-threaded, self-scheduling processor2021 11,048,656Multi-threaded, self-scheduling reconfigurable computing fabric2021 11,043,9523D stacked integrated circuits having failure management2021 11,010,161Multiple types of thread identifiers for a multi-threaded, self-scheduling reconfigurable computing fabric2021 11,003,451Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric2021 10,990,392Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric2021 10,990,391Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric2021 10,991,6843D stacked integrated circuits having functional blocks configured to provide redundancy sites2021 10,956,086Memory controller2021 10,949,347Multiple data channel memory module architecture2021 10,915,271Memory controller with programmable atomic operations2021 10,910,3663D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation2021 10,840,240Functional blocks implemented by 3D stacked integrated circuit2020 10,748,874Power and temperature management for functional blocks implemented by a 3D stacked integrated circuit2020 10,707,1973D stacked integrated circuits having functional blocks configured to provide redundancy sites2020 10,666,2643D stacked integrated circuits having failure management2020 10,606,693Memory controller implemented error correction code memory2020 10,534,591Multistage development workflow for generating a custom instruction set reconfigurable processor2020 10,461,0763D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation2019 10,430,190Systems and methods for selectively controlling multithreaded execution of executable code segments2019 10,223,081Multistate development workflow for generating a custom instruction set reconfigurable processor2019 10,061,699Multiple data channel memory module architecture2018 9,824,010'Multiple data channel memory module architecture'2017 9,710,384'Microprocessor architecture having alternative memory access paths'2017 9,449,659'Multiple data channel memory module architecture'2016 9,015,399'Multiple data channel memory module architecture'2015 8,972,958'Multistage development workflow for generating a custom instruction set reconfigurable processor'2015 8,561,037'Compiler for generating an executable comprising instructions for a plurality of different instruction sets'2013 8,443,147'Memory interleave for heterogeneous computing'2013 8,423,745'Systems and methods for mapping a neighborhood of data to general registers of a processing element'2013 8,315,175'Router switch fabric protection using forward error correction'2012 8,279,879'System and method for router data aggregation and delivery'2012 8,205,066'Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor'2012 8,156,307'Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set'2012 8,122,229'Dispatch mechanism for dispatching instructions from a host processor to a co-processor'2012 8,095,735'Memory interleave for heterogeneous computing'2012 7,974,208'System and method for router queue and congestion management'2011 7,813,365'System and method for router queue and congestion management'2010 7,613,183'System and method for router data aggregation and delivery'2009 7,324,500'Router network protection using multiple facility interfaces'2008 7,249,192'Protocol for insuring exactly once semantics of transactions across an unordered, unreliable network'2007 7,133,399'System and method for router central arbitration'2006 7,117,338'Virtual memory address translation control by TLB purge monitoring'2006 7,058,315'Fast decision threshold controller for burst-mode receiver'2006 7,002,980'System and method for router queue and congestion management'2006 6,999,411'System and method for router arbiter protection switching'2006 6,894,970'Router switch fabric protection using forward error correction'2005 6,879,559'Router line card protection using one-for-N redundancy'2005 6,876,657'System and method for router packet control and ordering'2005 6,711,357'Timing and synchronization for an IP router using an optical switch'2004 6,668,314'Virtual memory translation control by TLB purge monitoring'2003 6,397,365'Memory error correction using redundant sliced memory and standard ECC mechanisms'2002 6,081,876'Memory error containment in network cache environment via restricted access'2000 5,966,733'Optimizing data movement with hardware operations'1999 5,933,857'Accessing multiple independent microkernels existing in a globally shared memory system'1999 5,905,869'Time of century counter synchronization using a SCI interconnect'1999 5,859,975'Parallel processing computer system having shared coherent memory and interconnections utilizing separate undirectional request and response lines for direct communication or using crossbar switching device'1999 5,832,254'Scalable resynchronization of remote counters'1998 5,577,204'Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device'1996 5,560,027'Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes'1996 4,884,244'Method of addressing a computer memory'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989Based in Raleigh, NC, US· patent location history

1996–1999Based in Dallas, TX, US· patent location history

1998–2002Patents assigned to HEWLETT PACKARD CO (7)· patent assignee history

1998–2021Based in Plano, TX, US· patent location history

1999Based in Richardson, TX, US· patent location history

2004–2006Patents assigned to CHIARO NETWORKS LTD (8)· patent assignee history

2012–2015Patents assigned to CONVEY COMP (9)· patent assignee history

2012–2017Patents assigned to BREWER TONY (7)· patent assignee history

2016–2021Patents assigned to MICRON TECHNOLOGY INC (34)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	34	2016–2021
CONVEY COMP	9	2012–2015
CHIARO NETWORKS LTD	8	2004–2006
BREWER TONYself	7	2012–2017
HEWLETT PACKARD CO	7	1998–2002

Locations

Location	Patents	Span
Plano, Texas, US	65	1998–2021
Dallas, Texas, US	3	1996–1999
Richardson, Texas, US	1	1999
Raleigh, NC, US	1	1989