Inventor
Sergio Camerlo
Inventor
Cupertino, CA, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits39%
G06FElectric digital data processing25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y02PClimate change mitigation technologies in the production or processing of goods7%
Y10TTechnical subjects covered by former us classification7%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact4%
G05FSystems for regulating electric or magnetic variables4%
H01RElectrically-conductive connections4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
8,035,038'Method for fabricating a printed circuit board having a coaxial via'20117,574,687'Method and system to optimize timing margin in a system in package module'20097,404,250'Method for fabricating a printed circuit board having a coaxial via'20087,185,821'Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrate'20077,154,761'Techniques for distributing current in a backplane assembly and methods for making the same'20067,098,408'Techniques for mounting an area array package to a circuit board using an improved pad layout'20067,053,314'Methods and apparatus for providing a signal to a circuit board component'20066,914,780'Methods and apparatus for cooling a circuit board component using a heat pipe assembly'20056,204,712'Method and apparatus for clock uncertainty minimization'20016,157,251'Method and apparatus for clock uncertainty minimization'20006,157,250'Method and apparatus for clock uncertainty minimization with a clean power source'20006,081,106'Voltage setpoint error reduction'20006,069,539'VTT power distribution system'20006,052,012'Method and apparatus for clock uncertainly minimization'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2005Patents assigned to CISCO TECH IND (7)· patent assignee history
2000–2011Based in Cupertino, CA, US· patent location history
2006–2011Patents assigned to CISCO TECH INC (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CISCO TECH INC | 7 | 2006–2011 |
| CISCO TECH IND | 7 | 2000–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 14 | 2000–2011 |