Inventor

Stephen R. Van Doren

Inventor

Northborough, MA, US

Overview

61→

Patents

1996–2020

Patent span

Physics

Primary field (CPC G)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing94%

H04LTransmission of digital information, e.g. telegraphic communication3%

G11CStatic stores2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

10,705,961Scalably mechanism to implement an instruction that monitors for writes to an address2020 10,579,551Memory pressure notifier2020 10,572,260Spatial and temporal merging of remote atomic operations2020 10,445,271Multi-core communication acceleration using hardware queue device2019 10,437,616Method, apparatus, system for optimized work submission to an accelerator work queue2019 10,296,459Remote atomic operations in multi-socket systems2019 10,216,668Technologies for a distributed hardware queue manager2019 10,102,380Method and apparatus to provide secure application execution2018 9,418,009'Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory'2016 9,087,200'Method and apparatus to provide secure application execution'2015 8,468,308'System and method for non-migratory requests in a cache coherency protocol'2013 8,176,259'System and method for resolving transactions in a cache coherency protocol'2012 8,145,847'Cache coherency protocol with ordering points'2012 8,090,914'System and method for creating ordering points'2012 7,856,534'Transaction references for requests in a multi-processor network'2010 7,818,391'System and method to facilitate ordering point migration'2010 7,769,959'System and method to facilitate ordering point migration to memory'2010 7,620,696'System and method for conflict responses in a cache coherency protocol'2009 7,395,374'System and method for conflict responses in a cache coherency protocol with ordering point migration'2008 7,380,107'Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss'2008 7,376,794'Coherent signal in a multi-processor system'2008 7,203,775'System and method for avoiding deadlock'2007 7,177,987'System and method for responses between different cache coherency protocols'2007 7,174,431'Mechanism for resolving ambiguous invalidates in a computer system'2007 7,149,852'System and method for blocking data responses'2006 7,143,245'System and method for read migratory optimization in a cache coherency protocol'2006 7,051,163'Directory structure permitting efficient write-backs in a shared memory computer system'2006 7,024,520'System and method enabling efficient cache line reuse in a computer system'2006 7,003,635'Generalized active inheritance consistency mechanism having linked writes'2006 7,000,080'Channel-based late race resolution mechanism for a computer system'2006 6,990,559'Mechanism for resolving ambiguous invalidates in a computer system'2006 6,961,825'Cache coherency mechanism using arbitration masks'2005 6,904,465'Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch'2005 6,898,676'Computer system supporting both dirty-shared and non-dirty-shared data processing entities'2005 6,895,476'Retry-based late race resolution mechanism for a computer system'2005 6,892,290'Linked-list early race resolution mechanism'2005 6,801,986'Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation'2004 6,636,948'Method and system for a processor to gain assured ownership of an up-to-date copy of data'2003 6,353,876'Cache memory exchange optimized memory organization for a computer system'2002 6,286,090'Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches'2001 6,256,694'Distributed early arbitration'2001 6,249,846'Distributed data dependency stall mechanism'2001 6,209,065'Mechanism for optimizing generation of commit-signals in a distributed shared-memory system'2001 6,202,126'Victimization of clean data blocks'2001 6,185,654'Phantom resource memory address mapping system'2001 6,125,429'Cache memory exchange optimized memory organization for a computer system'2000 6,108,737'Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system'2000 6,105,108'Method and apparatus for releasing victim data buffers of computer systems by comparing a probe counter with a service counter'2000 6,088,771'Mechanism for reducing latency of memory barrier operations on a multiprocessor system'2000 6,085,263'Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor'2000 6,085,294'Distributed data dependency stall mechanism'2000 6,076,129'Distributed data bus sequencing for a system bus with separate address and data bus protocols'2000 6,061,765'Independent victim data buffer and probe buffer release control utilzing control flag'2000 6,055,605'Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches'2000 5,848,258'Memory bank addressing scheme'1998 5,761,731'Method and apparatus for performing atomic transactions in a shared memory multi processor system'1998 5,758,106'Arbitration unit which requests control of the system bus prior to determining whether such control is required'1998 5,737,546'System bus with separate address and data bus protocols'1998 5,666,551'Distributed data bus sequencing for a system bus with separate address and data bus protocols'1997 5,566,325'Method and apparatus for adaptive memory access'1996 5,537,575'System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2000Patents assigned to DIGITAL EQUIPMENT CORP (8)· patent assignee history

1996–2001Based in Shrewsbury, MA, US· patent location history

2000–2001Patents assigned to COMPAQ COMPUTER CORP (13)· patent assignee history

2000–2013Based in Northborough, MA, US· patent location history

2003–2013Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (28)· patent assignee history

2012–2020Patents assigned to VAN DOREN STEPHEN R (6)· patent assignee history

2015–2020Patents assigned to INTEL CORP (10)· patent assignee history

2015–2020Based in Portland, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HEWLETT PACKARD DEVELOPMENT CO	28	2003–2013
COMPAQ COMPUTER CORP	13	2000–2001
INTEL CORP	10	2015–2020
DIGITAL EQUIPMENT CORP	8	1996–2000
VAN DOREN STEPHEN Rself	6	2012–2020

Locations

Location	Patents	Span
Northborough, Massachusetts, US	42	2000–2013
Portland, OR, US	10	2015–2020
Shrewsbury, Massachusetts, US	9	1996–2001