Inventor
Abhijit Ray
Inventor
New Delhi, IN
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
A61Pprimary
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations28%
C07DHeterocyclic compounds23%
H03KPulse technique7%
A61KPreparations for medical, dental or toiletry purposes5%
C12NMicroorganisms or enzymes5%
G11CStatic stores5%
B82YSpecific uses or applications of nanostructures2%
C07CAcyclic or carbocyclic compounds2%
C07HSugars2%
G05FSystems for regulating electric or magnetic variables2%
PatentTitleYear
9,434,610'HPMA—docetaxel conjugates and uses therefore'20168,710,261'5-phenyl-pentanoic acid derivatives as matrix metalloproteinase inhibitors for the treatment of asthma and other diseases'20148,420,666'Pyrazolo (3, 4-B) pyridine derivatives as phosphodiesterase inhibitors'20137,915,286'Substituted pyrazolo [3,4-b] pyridines as phosphodiesterase inhibitors'20117,825,147'Inhibitors of phosphodiesterase type-IV'20107,790,689'Monosaccharide derivatives'20107,781,460'Substituted indazoles as inhibitors of phosphodiesterase type-IV'20107,750,735'Voltage-level translator'20107,747,425'System and method for peak current modeling for an IC design'20107,741,882'Current-limited output buffer'20107,688,111'Level-shifting circuit with bipolar junction transistor'20107,674,811'5-lipoxygenase inhibitors'20107,629,812'Switching circuits and methods for programmable logic devices'20097,468,366'Cytotoxic agents'20087,319,105'Cytotoxic agents'20087,027,548'Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings'20066,956,040'Oxazolidinone piperazinyl derivatives as potential antimicrobials'20056,734,307'Oxazolidinone derivatives as antimicrobials'20046,476,666'Bootstrapped charge pump'20026,225,824'High speed output buffer for high/low voltage operation'20016,175,520'Nonvolatile memory array having local program load line repeaters'20016,097,179'Temperature compensating compact voltage regulator for integrated circuit device'20006,016,270'Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2006Patents assigned to ALLIANCE SEMICONDUCTOR CORP (4)· patent assignee history
2000–2006Based in Santa Clara, CA, US· patent location history
2004–2014Patents assigned to RANBAXY LAB LTD (9)· patent assignee history
2004–2014Based in New Delhi, IN· patent location history
2008Based in Orissa, IN· patent location history
2009–2010Based in Sunnyvale, CA, US· patent location history
2010Patents assigned to SUVOLTA INC (3)· patent assignee history
2010Based in Delhi, IN· patent location history
2013–2016Patents assigned to RAY ABHIJIT (3)· patent assignee history
2013–2014Patents assigned to DASTIDAR SUNANDA G (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RANBAXY LAB LTD | 9 | 2004–2014 |
| ALLIANCE SEMICONDUCTOR CORP | 4 | 2000–2006 |
| RAY ABHIJITself | 3 | 2013–2016 |
| SUVOLTA INC | 3 | 2010 |
| DASTIDAR SUNANDA G | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Delhi, IN | 6 | 2004–2014 |
| Sunnyvale, California, US | 5 | 2009–2010 |
| Santa Clara, California, US | 3 | 2000–2006 |
| Delhi, IN | 2 | 2010 |
| Orissa, IN | 2 | 2008 |