Inventor
Kimin JUN
Inventor
US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10DInorganic electric semiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10BElectronic memory devices7%
B82YSpecific uses or applications of nanostructures2%
H05KPrinted circuits2%
H01FMagnets1%
H10NElectric solid-state devices not otherwise provided for1%
G01RMeasuring electric variables1%
PatentTitleYear
12,581,968Package architecture of large dies using quasi-monolithic chip layers202612,581,938Package architecture for quasi-monolithic chip with backside power202612,538,841Quasi-monolithic die architectures202612,526,985Back-side reveal for power delivery to backend memory with frontend transistors and backend memroy cells202612,500,207Packaging architecture with intermediate routing layers202512,469,630Inductor and transformer semiconductor devices using hybrid bonding technology202512,463,180Monolithic chip stacking using a die with double-sided interconnect layers202512,456,702Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets202512,417,978Microelectronic assemblies having backside die-to-package interconnects202512,406,956Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers202512,375,060Digitally controlled lithographically-defined multi-frequency acoustic resonators202512,362,325Monolithic chip stacking using a die with double-sided interconnect layers202512,300,579Liquid cooled interposer for integrated circuit stack202512,288,810Backside contact structures and fabrication for metal on both sides of devices202512,266,682Capacitors and resistors at direct bonding interfaces in microelectronic assemblies202512,266,570Self-aligned interconnect structures and methods of fabrication202512,199,018Direct bonding in microelectronic assemblies202512,176,323Microelectronic assemblies202412,107,060Microelectronic assemblies with inductors in direct bonding regions202412,100,761Wrap-around source/drain method of making contacts for backside metals202412,100,762Wrap-around source/drain method of making contacts for backside metals202412,062,631Microelectronic assemblies with inductors in direct bonding regions202411,996,404Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material202411,935,933Backside contact structures and fabrication for metal on both sides of devices202411,869,894Metallization structures for stacked device connectivity and their methods of fabrication202411,854,894Integrated circuit device structures and double-sided electrical testing202311,784,165Monolithic chip stacking using a die with double-sided interconnect layers202311,721,649Microelectronic assemblies202311,676,966Stacked transistors having device strata with different channel widths202311,658,221Backside contact structures and fabrication for metal on both sides of devices202311,640,961III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts202311,605,565Three dimensional integrated circuits with stacked transistors202311,594,524Fabrication and use of through silicon vias on double sided interconnect device202311,594,452Techniques for revealing a backside of an integrated circuit device, and associated configurations202311,569,238Vertical memory cells202311,552,104Stacked transistors with dielectric between channels of different device strata202311,532,719Transistors on heterogeneous bonding layers202211,482,621Vertically stacked CMOS with upfront M0 interconnect202211,430,814Metallization structures for stacked device connectivity and their methods of fabrication202211,393,777Microelectronic assemblies202211,393,818Stacked transistors with Si PMOS and high mobility thin film transistor NMOS202211,348,897Microelectronic assemblies202211,264,493Wrap-around source/drain method of making contacts for backside metals202211,251,156Fabrication and use of through silicon vias on double sided interconnect device202211,251,158Monolithic chip stacking using a die with double-sided interconnect layers202211,244,943Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material202211,201,221Backside contact structures and fabrication for metal on both sides of devices2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (47)· patent assignee history
2021–2026Based in US· patent location history
2024Patents assigned to INTEL CORPROATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 47 | 2021–2026 |
| INTEL CORPROATION | 1 | 2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 47 | 2021–2026 |