Inventor
Neal R. Mielke
Inventor
Los Altos Hills, CA, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores57%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
G06FElectric digital data processing11%
H10BElectronic memory devices11%
H10DInorganic electric semiconductor devices5%
G11BInformation storage based on relative movement between record carrier and transducer3%
PatentTitleYear
10,658,053Ramping inhibit voltage during memory programming20209,792,997'Ramping inhibit voltage during memory programming'20179,740,437'Mechanism to adapt garbage collection resource allocation in a solid state drive'20179,418,752'Ramping inhibit voltage during memory programming'20168,650,353'Apparatus, system, and method for refreshing non-volatile memory'20148,595,422'Memory devices and methods of storing data on a memory device'20138,400,831'Method and apparatus for improving endurance of flash memories'20138,230,158'Memory devices and methods of storing data on a memory device'20127,835,187'Boosting seed voltage for a memory device'20106,943,071'Integrated memory cell and method of fabrication'20056,518,618'Integrated memory cell and method of fabrication'20036,376,899'Planar guard ring'20026,137,155'Planar guard ring'20005,977,639'Metal staples to prevent interlayer delamination'19995,566,194'Method and apparatus to improve read reliability in semiconductor memories'19965,455,800'Apparatus and a method for improving the program and erase performance of a flash EEPROM memory array'19955,452,311'Method and apparatus to improve read reliability in semiconductor memories'19955,386,388'Single cell reference scheme for flash memory sensing and program state verification'19955,377,147'Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy'19945,347,489'Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy'19945,339,272'Precision voltage reference'19945,327,383'Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy'19945,309,012'Protected erase voltage discharge transistor in a nonvolatile semiconductor memory'19945,301,150'Flash erasable single poly EPROM device'19945,245,570'Floating gate non-volatile memory blocks and select transistors'19935,239,505'Floating gate non-volatile memory with blocks and memory refresh'19935,237,535'Method of repairing overerased cells in a flash memory'19935,220,528'Compensation circuit for leakage in flash EPROM'19934,963,825'Method of screening EPROM-related devices for endurance failure'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2020Patents assigned to INTEL CORP (27)· patent assignee history
1990Based in Redwood City, CA, US· patent location history
1993–2020Based in Los Altos Hills, CA, US· patent location history
1993Based in Los Altos, CA, US· patent location history
2012–2013Patents assigned to MICRON TECHNOLOGY INC (2)· patent assignee history
2012–2013Patents assigned to MIELKE NEAL (2)· patent assignee history
2013–2016Patents assigned to MIELKE NEAL R (3)· patent assignee history
2013–2016Patents assigned to KALAVADE PRANAV (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 1990–2020 |
| MIELKE NEAL Rself | 3 | 2013–2016 |
| KALAVADE PRANAV | 2 | 2013–2016 |
| MICRON TECHNOLOGY INC | 2 | 2012–2013 |
| MIELKE NEALself | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos Hills, California, US | 27 | 1993–2020 |
| Los Altos, California, US | 1 | 1993 |
| Redwood City, California, US | 1 | 1990 |