Inventor
Kouichi Kumagai
Inventor
Tokyo, JP
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
G11CStatic stores15%
H03KPulse technique15%
F16DCouplings for transmitting rotation6%
F21KNon-electric light sources using luminescence3%
F21VFunctional features or details of lighting devices or systems thereof3%
F21YIndexing scheme associated with subclasses f21k, f21l, f21s and f21v, relating to the form or the kind of the light sources or of the colour of the light emitted3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
G06FElectric digital data processing3%
H05KPrinted circuits3%
PatentTitleYear
8,610,141'Three-dimensional LED substrate and LED lighting device'20136,719,114'Clutch outer'20046,643,840'Designing method of semiconductor integrated circuit using library storing mask pattern of macro circuit and designing apparatus executing the same'20036,505,717'Clutch weight for wet centrifugal clutch and process for producing the same'20036,414,357'Master-slice type semiconductor IC device with different kinds of basic cells'20026,404,254'Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude'20026,255,862'Latch type sense amplifier circuit'20016,243,284'Multivalued mask read-only memory'20016,208,170'Semiconductor integrated circuit having a sleep mode with low power and small area'20016,208,171'Semiconductor integrated circuit device with low power consumption and simple manufacturing steps'20016,188,111'Dual gate semiconductor device for shortening channel length'20016,140,161'Semiconductor integrated circuit device and method for making the same'20006,134,154'Semiconductor memory device with several access enabled using single port memory cell'20006,100,720'Low dissipation inverter circuit'20006,057,568'Application specific integrated circuit semiconductor device having MOS transistor with reduced gate resistance'20006,037,617'SOI IGFETs having raised integration level'20006,008,510'Silicon on insulator master slice semiconductor integrated circuit'19995,998,879'Semiconductor memory device'19995,754,068'CMOS logic LSI having a long internal wiring conductor for signal transmission'19985,608,240'Semiconductor integrated circuit having at least one asymmetrical CMOS transistor'19975,561,388'Semiconductor device having CMOS circuit and bipolar circuit mixed'19965,473,182'Semiconductor device'19955,397,906'Gate array integrated semiconductor device having stabilized power supply potentials'19955,168,341'Bipolar-CMOS integrated circuit having a structure suitable for high integration'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2002Patents assigned to NEC CORP (20)· patent assignee history
1992–2003Based in Tokyo, JP· patent location history
2003–2004Patents assigned to FCC KK (2)· patent assignee history
2003Based in Shizouka, JP· patent location history
2004Based in Shizuoka, JP· patent location history
2013Patents assigned to INOUE TAKUYA (1)· patent assignee history
2013Patents assigned to KUMAGAI KOUICHI (1)· patent assignee history
2013Patents assigned to KUNIEDA TAKAHA (1)· patent assignee history
2013Based in Yokohama, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 20 | 1992–2002 |
| FCC KK | 2 | 2003–2004 |
| INOUE TAKUYA | 1 | 2013 |
| KUMAGAI KOUICHIself | 1 | 2013 |
| KUNIEDA TAKAHA | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 21 | 1992–2003 |
| Yokohama, JP | 1 | 2013 |
| Shizuoka, JP | 1 | 2004 |
| Shizouka, JP | 1 | 2003 |