Inventor
Xavier F. BRUN
Inventor
US
Overview
Patents· 3 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
G02BOptical elements, systems or apparatus10%
H10DInorganic electric semiconductor devices10%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation10%
H10HInorganic light-emitting semiconductor devices having potential barriers10%
PatentTitleYear
12,599,050Multi-level die coupled with a substrate202611,804,470Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control202311,705,417Backside metallization (BSM) on stacked die packages and external silicon at wafer level, singulated die level, or stacked dies level2023Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2023–2026Patents assigned to INTEL CORP (3)· patent assignee history
2023–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 3 | 2023–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 3 | 2023–2026 |