Inventor

Girish A. Dixit

Inventor

San Jose, CA, US

Overview

1992–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%

C23CCoating metallic material11%

H10DInorganic electric semiconductor devices9%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H01JElectric discharge tubes or discharge lamps4%

C25DProcesses for the electrolytic or electrophoretic production of coatings3%

C07DHeterocyclic compounds3%

A61KPreparations for medical, dental or toiletry purposes2%

A61PSpecific therapeutic activity of chemical compounds or medicinal preparations1%

PatentTitleYear

11,048,174Method of controlling a patterning process, lithographic apparatus, metrology apparatus lithographic cell and associated computer program2021 10,192,742Soft landing nanolaminates for advanced patterning2019 9,905,423'Soft landing nanolaminates for advanced patterning'2018 9,390,909'Soft landing nanolaminates for advanced patterning'2016 9,227,958'Amorphous and crystalline forms of aprepitant and processes for the preparation thereof'2016 9,006,443'Process for preparing quinoline-3-carboxamide derivatives'2015 8,858,763'Apparatus and methods for deposition and/or etch selectivity'2014 8,552,194'Process for preparing quinoline-3-carboxamide derivatives'2013 8,354,428'Solid state forms of laquinimod and its sodium salt'2013 8,342,119'Self aligning non contact shadow ring process kit'2013 8,314,235'Process for preparing varenicline, varenicline intermediates, pharmaceutically acceptable salts thereof'2012 8,268,722'Interfacial capping layers for interconnects'2012 8,124,522'Reducing UV and dielectric diffusion barrier interaction through the modulation of optical properties'2012 8,101,597'Quetiapine salts and their polymorphs'2012 8,062,977'Ternary tungsten-containing resistive thin films'2011 8,017,523'Deposition of doped copper seed layers having improved reliability'2011 7,848,839'System, method, and medium for an endpoint detection scheme for copper low-dielectric damascene structures for improved dielectric and copper loss'2010 7,727,882'Compositionally graded titanium nitride film for diffusion barrier applications'2010 7,510,634'Apparatus and methods for deposition and/or etch selectivity'2009 7,425,716'Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to a large area electron beam'2008 7,205,228'Selective metal encapsulation schemes'2007 7,115,534'Dielectric materials to prevent photoresist poisoning'2006 7,018,941'Post treatment of low k dielectric films'2006 6,991,709'Multi-step magnetron sputtering process'2006 6,962,883'Integrated circuit insulator and method'2005 6,951,599'Electropolishing of metallic interconnects'2005 6,913,680'Method of application of electrical biasing to enhance metal deposition'2005 6,905,622'Electroless deposition method'2005 6,899,816'Electroless deposition method'2005 6,878,245'Method and apparatus for reducing organic depletion during non-processing time periods'2005 6,869,516'Method for removing electrolyte from electrical contacts and wafer touching areas'2005 6,824,666'Electroless deposition method over sub-micron apertures'2004 6,824,612'Electroless plating system'2004 6,821,909'Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application'2004 6,808,611'Methods in electroanalytical techniques to analyze organic components in plating baths'2004 6,797,620'Method and apparatus for improved electroplating fill of an aperture'2004 6,787,006'Operating a magnetron sputter reactor in two modes'2004 6,773,569'Potential pulse-scan methods of analyzing organic additives in plating baths with multi-component additives'2004 6,746,591'ECP gap fill by modulating the voltate on the seed layer to increase copper concentration inside feature'2004 6,617,242'Method for fabricating interlevel contacts of aluminum/refractory metal alloys'2003 6,610,189'Method and associated apparatus to mechanically enhance the deposition of a metal film within a feature'2003 6,589,865'Low pressure, low temperature, semiconductor gap filling process'2003 6,589,352'Self aligning non contact shadow ring process kit'2003 6,566,258'Bi-layer etch stop for inter-level via'2003 6,485,618'Integrated copper fill process'2002 6,451,177'Vault shaped target and magnetron operable in two sputtering modes'2002 6,358,849'Integrated circuit interconnect and method'2002 6,355,559'Passivation of inlaid metallization'2002 6,355,558'Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films'2002 6,333,265'Low pressure, low temperature, semiconductor gap filling process'2001 6,303,452'Method for making transistor spacer etch pinpoint structure'2001 6,297,125'Air-bridge integration scheme for reducing interconnect delay'2001 6,287,963'Method for forming a metal contact'2001 6,277,249'Integrated process for copper via filling using a magnetron and target producing highly energetic ions'2001 6,274,008'Integrated process for copper via filling'2001 6,268,297'Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces'2001 6,251,771'Hydrogen passivation of chemical-mechanically polished copper-containing layers'2001 6,242,811'Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature'2001 6,194,313'Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process'2001 6,159,847'Multilayer metal structure for improved interconnect reliability'2000 6,130,156'Variable doping of metal plugs for enhanced reliability'2000 6,069,072'CVD tin barrier layer for reduced electromigration of aluminum plugs'2000 5,930,673'Method for forming a metal contact'1999 5,856,233'Method of forming a field programmable device'1999 5,849,367'Elemental titanium-free liner and fabrication process for inter-metal connections'1998 5,847,457'Structure and method of forming vias'1998 5,759,869'Method to imporve metal step coverage by contact reflow'1998 5,593,921'Method of forming vias'1997 5,582,971'Method of forming submicron contacts'1996 5,578,872'Planar contact with a void'1996 5,571,752'Method of forming a planar contact with a void'1996 5,523,624'Integrated circuit device structure with dielectric and metal stacked plug in contact hole'1996 5,521,411'Transistor spacer etch pinpoint structure'1996 5,510,294'Method of forming vias for multilevel metallization'1996 5,493,144'Field progammable device with contact openings'1996 5,491,355'Self-aligned contact formation'1996 5,444,019'Semiconductor contact via structure and method'1995 5,440,166'Planarized isolation structure for CMOS devices'1995 5,391,520'Method for forming local interconnect for integrated circuits'1995 5,369,302'Method to improve step coverage by contact reflow'1994 5,348,901'Interconnect and resistor for integrated circuits'1994 5,319,245'Local interconnect for integrated circuits'1994 5,317,192'Semiconductor contact via structure having amorphous silicon side walls'1994 5,285,103'Structure and method for contacts in CMOS devices'1994 5,278,098'Method for self-aligned polysilicon contact formation'1994 5,244,827'Method for planarized isolation for CMOS devices'1993 5,233,135'Interconnect for integrated circuits'1993 5,182,627'Interconnect and resistor for integrated circuits'1993 5,164,340'Structure and method for contacts in CMOS devices'1992 5,108,951'Method for forming a metal contact'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–1998Patents assigned to SGS THOMSON MICROELECTRONICS (24)· patent assignee history

1992–2003Based in Dallas, TX, US· patent location history

1998–2005Patents assigned to TEXAS INSTRUMENTS INC (14)· patent assignee history

1998–2005Based in Plano, TX, US· patent location history

2001–2013Patents assigned to APPLIED MATERIALS INC (28)· patent assignee history

2001–2021Based in San Jose, CA, US· patent location history

2009–2019Patents assigned to NOVELLUS SYSTEMS INC (10)· patent assignee history

2011–2016Patents assigned to DIXIT GIRISH (9)· patent assignee history

2012–2015Based in Uttar Pradesh, IN· patent location history

2016Based in Navi Mumbai, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
APPLIED MATERIALS INC	28	2001–2013
SGS THOMSON MICROELECTRONICS	24	1992–1998
TEXAS INSTRUMENTS INC	14	1998–2005
NOVELLUS SYSTEMS INC	10	2009–2019
DIXIT GIRISHself	9	2011–2016

Locations

Location	Patents	Span
San Jose, California, US	41	2001–2021
Dallas, Texas, US	31	1992–2003
Plano, Texas, US	12	1998–2005
Uttar Pradesh, IN	4	2012–2015
Navi Mumbai, IN	1	2016