Inventor

Eric A. Foreman

Inventor

Fairfax, VT, US

Overview

2006–2021

Patent span

Physics

Primary field (CPC G)

Patents· 89 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing75%

G01RMeasuring electric variables11%

Y02PClimate change mitigation technologies in the production or processing of goods3%

G01CMeasuring distances, levels or bearings2%

G05FSystems for regulating electric or magnetic variables2%

G08GTraffic control systems2%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

G11CStatic stores1%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%

PatentTitleYear

10,970,448Partial parameters and projection thereof included within statistical timing analysis2021 10,747,925Variable accuracy incremental timing analysis2020 10,691,853Superposition of canonical timing value representations in statistical static timing analysis2020 10,606,970Selection of corners and/or margins using statistical static timing analysis of an integrated circuit2020 10,546,095Parameter collapsing and corner reduction in an integrated circuit2020 10,489,540Integrating manufacturing feedback into integrated circuit structure design2019 10,409,938Method of parameter creation2019 10,393,532Emergency responsive navigation2019 10,394,982Partial parameters and projection thereof included within statistical timing analysis2019 10,380,286Multi-sided variations for creating integrated circuits2019 10,380,289Multi-sided variations for creating integrated circuits2019 10,372,851Independently projecting a canonical clock2019 10,354,047Parameter collapsing and corner reduction in an integrated circuit2019 10,346,569Multi-sided variations for creating integrated circuits2019 10,296,704Parameter collapsing and corner reduction in an integrated circuit2019 10,289,776Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit2019 10,222,852Voltage and frequency balancing at nominal point2019 10,222,850Voltage and frequency balancing at nominal point2019 10,216,252Voltage and frequency balancing at nominal point2019 10,169,502Addressing of process and voltage points2019 10,055,532Collapsing terms in statistical static timing analysis2018 10,049,570Controlling right-of-way for priority vehicles2018 10,037,402Parameter collapsing and corner reduction in an integrated circuit2018 10,031,985Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit2018 10,013,516Selection of corners and/or margins using statistical static timing analysis of an integrated circuit2018 9,959,382Adaptive characterization and instantiation of timing abstracts2018 9,939,880Voltage and frequency balancing at nominal point2018 9,858,368'Integrating manufacturing feedback into integrated circuit structure design'2018 9,767,239'Timing optimization driven by statistical sensitivites'2017 9,646,122'Variable accuracy parameter modeling in statistical timing'2017 9,619,609'Integrated circuit chip design methods and systems using process window-aware timing analysis'2017 9,594,868'Scaling voltages in relation to die location'2017 9,569,571'Method and system for timing violations in a circuit'2017 9,552,447'Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling'2017 9,519,747'Dynamic and adaptive timing sensitivity during static timing analysis using look-up table'2016 9,501,609'Selection of corners and/or margins using statistical static timing analysis of an integrated circuit'2016 9,495,497'Dynamic voltage frequency scaling'2016 9,483,604'Variable accuracy parameter modeling in statistical timing'2016 9,430,603'Scaling voltages in relation to die location'2016 9,378,328'Modeling multi-patterning variability with statistical timing'2016 9,348,962'Hierarchical design of integrated circuits with multi-patterning requirements'2016 9,269,407'System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time'2016 9,262,569'Balancing sensitivities with respect to timing closure for integrated circuits'2016 9,171,124'Parasitic extraction in an integrated circuit with multi-patterning requirements'2015 9,157,956'Adaptive power control using timing canonicals'2015 8,963,620'Controlling circuit voltage and frequency based upon location-dependent temperature'2015 8,949,765'Modeling multi-patterning variability with statistical timing'2015 8,856,709'Systems and methods for correlated parameters in statistical static timing analysis'2014 8,850,380'Selective voltage binning within a three-dimensional integrated chip stack'2014 8,850,378'Hierarchical design of integrated circuits with multi-patterning requirements'2014 8,843,874'Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures'2014 8,839,167'Reducing runtime and memory requirements of static timing analysis'2014 8,839,165'Power/performance optimization through continuously variable temperature-based voltage control'2014 8,839,170'Power/performance optimization through temperature/voltage control'2014 8,832,625'Systems and methods for correlated parameters in statistical static timing analysis'2014 8,806,402'Modeling multi-patterning variability with statistical timing'2014 8,769,452'Parasitic extraction in an integrated circuit with multi-patterning requirements'2014 8,768,679'System and method for efficient modeling of NPskew effects on static timing tests'2014 8,719,763'Frequency selection with selective voltage binning'2014 8,707,233'Systems and methods for correlated parameters in statistical static timing analysis'2014 8,656,207'Method for modeling variation in a feedback loop of a phase-locked loop'2014 8,560,989'Statistical clock cycle computation'2013 8,543,960'Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures'2013 8,468,483'Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence'2013 8,458,632'Efficient slack projection for truncated distributions'2013 8,448,110'Method to reduce delay variation by sensitivity cancellation'2013 8,413,095'Statistical single library including on chip variation for rapid timing and power analysis'2013 8,141,014'System and method for common history pessimism relief during static timing analysis'2012 8,141,025'Method of performing timing analysis on integrated circuit chips with consideration of process variations'2012 8,141,012'Timing closure on multiple selective corners in a single statistical timing run'2012 8,108,816'Device history based delay variation adjustment during static timing analysis'2012 8,086,988'Chip design and fabrication method optimized for profit'2011 8,056,035'Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing'2011 7,962,874'Method and system for evaluating timing in an integrated circuit'2011 7,886,246'Methods for identifying failing timing requirements in a digital design'2011 7,873,926'Methods for practical worst test definition and debug during block based statistical static timing analysis'2011 7,870,525'Slack sensitivity to parameter variation based timing analysis'2011 7,844,932'Method to identify timing violations outside of manufacturing specification limits'2010 7,797,657'Parameter ordering for multi-corner static timing analysis'2010 7,784,003'Estimation of process variation impact of slack in multi-corner path-based static timing analysis'2010 7,750,648'Method to quickly estimate inductance for timing models'2010 7,716,616'Slack sensitivity to parameter variation based timing analysis'2010 7,681,157'Variable threshold system and method for multi-corner static timing analysis'2010 7,620,921'IC chip at-functional-speed testing with process coverage evaluation'2009 7,555,740'Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis'2009 7,444,608'Method and system for evaluating timing in an integrated circuit'2008 7,401,307'Slack sensitivity to parameter variation based timing analysis'2008 7,181,711'Prioritizing of nets for coupled noise analysis'2007 7,089,143'Method and system for evaluating timing in an integrated circuit'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2021Patents assigned to IBM (84)· patent assignee history

2006–2021Based in Fairfax, VT, US· patent location history

2011–2018Patents assigned to FOREMAN ERIC A (17)· patent assignee history

2011–2018Patents assigned to HABITZ PETER A (15)· patent assignee history

2012–2018Patents assigned to HEMMETT JEFFREY G (11)· patent assignee history

2012Based in Essex Junction, VT, US· patent location history

2015–2018Patents assigned to GLOBALFOUNDRIES INC (9)· patent assignee history

2015Based in Faifax, VT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	84	2006–2021
FOREMAN ERIC Aself	17	2011–2018
HABITZ PETER A	15	2011–2018
HEMMETT JEFFREY G	11	2012–2018
GLOBALFOUNDRIES INC	9	2015–2018

Locations

Location	Patents	Span
Fairfax, VT, US	85	2006–2021
Essex Junction, VT, US	3	2012
Faifax, VT, US	1	2015