Inventor
Bikas Maiti
Inventor
Austin, TX, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
G11CStatic stores26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H03KPulse technique6%
H10BElectronic memory devices6%
G06FElectric digital data processing3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
11,005,461Level shift latch circuitry202110,854,280Read assist circuitry for memory applications202010,839,934Redundancy circuitry for memory application202010,008,260Clock generation circuitry for memory applications20189,997,217Write assist circuitry20189,064,559'Memory device and method of performing access operations within such a memory device'20158,611,172'Controlling a voltage level of an access signal to reduce access disturbs in semiconductor memories'20138,264,896'Integrated circuit having an array supply voltage control circuit'20128,116,153'Read only memory and method of reading same'20126,376,349'Process for forming a semiconductor device and a conductive structure'20026,255,204'Method for forming a semiconductor device'20016,171,910'Method for forming a semiconductor device'20016,084,279'Semiconductor device having a metal containing layer overlying a gate dielectric'20006,049,114'Semiconductor device having a metal containing layer overlying a gate dielectric'20006,027,961'CMOS semiconductor devices and method of formation'20006,020,024'Method for forming high dielectric constant metal oxides'20005,885,870'Method for forming a semiconductor device having a nitrided oxide dielectric layer'19995,861,347'Method for forming a high voltage gate dielectric for use in integrated circuit'19995,830,802'Process for reducing halogen concentration in a material layer during semiconductor device fabrication'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2002Patents assigned to MOTOROLA INC (10)· patent assignee history
1998–2021Based in Austin, TX, US· patent location history
2012–2013Patents assigned to MAITI BIKAS (3)· patent assignee history
2012Patents assigned to FREESCALE SEMICONDUCTOR INC (2)· patent assignee history
2013–2021Patents assigned to ADVANCED RISC MACH LTD (7)· patent assignee history
2013Patents assigned to CHEN HSIN-YU (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MOTOROLA INC | 10 | 1998–2002 |
| ADVANCED RISC MACH LTD | 7 | 2013–2021 |
| MAITI BIKASself | 3 | 2012–2013 |
| FREESCALE SEMICONDUCTOR INC | 2 | 2012 |
| CHEN HSIN-YU | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 19 | 1998–2021 |