Inventor
Matthew Park
Inventor
Boise, ID, US
Overview
Patents· 10 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10BElectronic memory devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
B01LChemical or physical laboratory apparatus for general use4%
B41MPrinting, duplicating, marking, or copying processes4%
B82YSpecific uses or applications of nanostructures4%
G01QScanning-probe techniques or apparatus4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G06GAnalogue computers4%
PatentTitleYear
10,727,242Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor202010,720,446Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus202010,672,657Semiconductor device structures including stair step structures, and related semiconductor devices202010,453,748Methods of forming semiconductor device structures including stair step structures201910,263,007Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor201910,157,933Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus201810,014,309Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor20187,954,166'Independently-addressable, self-correcting inking for cantilever arrays'20117,792,185'Methods and apparatus for calibrating output voltage levels associated with current-integrating summing amplifier'20107,715,474'Decision feedback equalizer (DFE) architecture'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010Patents assigned to IBM (2)· patent assignee history
2010Based in Cambridge, MA, US· patent location history
2011Patents assigned to UNIV NORTHWESTERN (1)· patent assignee history
2011Based in Evanston, IL, US· patent location history
2018–2020Patents assigned to MICRON TECHNOLOGY INC (7)· patent assignee history
2018–2020Based in Boise, ID, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 7 | 2018–2020 |
| IBM | 2 | 2010 |
| UNIV NORTHWESTERN | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 7 | 2018–2020 |
| Cambridge, Massachusetts, US | 2 | 2010 |
| Evanston, Illinois, US | 1 | 2011 |