Inventor
Joerg Hohage
Inventor
Dresden, DE
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H10DInorganic electric semiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
C23CCoating metallic material3%
H01LSemiconductor devices3%
H05HPlasma technique2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
8,841,140'Technique for forming a passivation layer without a terminal metal'20148,828,888'Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer'20148,759,232'Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress'20148,546,274'Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material'20138,450,172'Non-insulating stressed material layers in a contact level of semiconductor devices'20138,338,284'Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer'20128,211,795'Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment'20128,153,524'Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices'20128,053,354'Reduced wafer warpage in semiconductors by stress engineering in the metallization system'20118,034,726'Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials'20117,994,072'Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device'20117,994,059'Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device'20117,938,973'Arc layer having a reduced flaking tendency and a method of manufacturing the same'20117,906,383'Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device'20117,875,561'Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material'20117,867,917'Etch stop layer for a metallization layer with enhanced adhesion, etch selectivity and hermeticity'20117,858,531'Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region'20107,678,699'Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction'20107,608,912'Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress'20097,550,396'Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device'20097,491,638'Method of forming an insulating capping layer for a copper metallization layer'20097,476,626'Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity'20097,396,718'Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress'20087,381,602'Method of forming a field effect transistor comprising a stressed channel region'20087,341,903'Method of forming a field effect transistor having a stressed channel region'20087,030,044'Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric'20067,022,602'Nitrogen-enriched low-k barrier layer for a copper metallization layer'20066,893,956'Barrier layer for a copper metallization layer including a low-k dielectric'20056,596,631'Method of forming copper interconnect capping layers with improved interface and adhesion'20036,569,768'Surface treatment and capping layer process for producing a copper interface in a semiconductor device'20036,368,948'Method of forming capped copper interconnects with reduced hillocks'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2014Patents assigned to ADVANCED MICRO DEVICES INC (25)· patent assignee history
2002–2014Based in Dresden, DE· patent location history
2011–2014Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history
2012–2014Patents assigned to HOHAGE JOERG (8)· patent assignee history
2012–2014Patents assigned to RUELKE HARTMUT (4)· patent assignee history
2013–2014Patents assigned to RICHTER RALF (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 25 | 2002–2014 |
| HOHAGE JOERGself | 8 | 2012–2014 |
| GLOBALFOUNDRIES INC | 6 | 2011–2014 |
| RUELKE HARTMUT | 4 | 2012–2014 |
| RICHTER RALF | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dresden, DE | 31 | 2002–2014 |