Inventor

Steven M. Douskey

Inventor

Rochester, MN, US

Overview

77→

Patents

1990–2021

Patent span

Physics

Primary field (CPC G)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary

G01RMeasuring electric variables56%

G06FElectric digital data processing29%

G11CStatic stores6%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%

G21KHandling of particles or ionising radiation not otherwise provided for2%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

H03KPulse technique1%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses1%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%

Y02PClimate change mitigation technologies in the production or processing of goods1%

PatentTitleYear

11,112,854Operating pulsed latches on a variable power supply2021 10,816,599Dynamically power noise adaptive automatic test pattern generation2020 10,386,912Operating pulsed latches on a variable power supply2019 10,379,159Minimization of over-masking in an on product multiple input signature register (OPMISR)2019 10,371,750Minimization of over-masking in an on product multiple input signature register (OPMISR)2019 10,371,749Removal of over-masking in an on product multiple input signature register (OPMISR) test2019 10,372,853Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)2019 10,359,471Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through scan skewing2019 10,345,380Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading2019 10,234,507Implementing register array (RA) repair using LBIST2019 10,067,183Portion isolation architecture for chip isolation test2018 10,060,978Implementing prioritized compressed failure defects for efficient scan diagnostics2018 10,060,971Adjusting latency in a scan cell2018 10,024,917Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through spreading in stumpmux daisy-chain structure2018 10,024,914Diagnosing failure locations of an integrated circuit with logic built-in self-test2018 10,001,523Adjusting latency in a scan cell2018 9,964,591Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation2018 9,746,516'Collecting diagnostic data from chips'2017 9,726,723'Scan chain processing in a partially functional chip'2017 9,575,120'Scan chain processing in a partially functional chip'2017 9,568,549'Managing redundancy repair using boundary scans'2017 9,557,383'Partitioned scan chain diagnostics using multiple bypass structures and injection points'2017 9,551,747'Inserting bypass structures at tap points to reduce latch dependency during scan testing'2017 9,547,039'Inserting bypass structures at tap points to reduce latch dependency during scan testing'2017 9,529,046'Partitioned scan chain diagnostics using multiple bypass structures and injection points'2016 9,429,621'Implementing enhanced scan chain diagnostics via bypass multiplexing structure'2016 9,429,622'Implementing enhanced scan chain diagnostics via bypass multiplexing structure'2016 9,404,969'Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies'2016 9,378,318'Shared channel masks in on-product test compression system'2016 9,372,232'Collecting diagnostic data from chips'2016 9,366,723'Test coverage of integrated circuits with masking pattern selection'2016 9,355,203'Shared channel masks in on-product test compression system'2016 9,297,856'Implementing MISR compression methods for test time reduction'2016 9,285,423'Managing chip testing data'2016 9,201,117'Managing redundancy repair using boundary scans'2015 9,188,636'Self evaluation of system on a chip with multiple cores'2015 9,151,800'Chip testing with exclusive OR'2015 9,134,373'Hierarchal test block test pattern reduction in on-product test compression system'2015 9,134,375'Hierarchal test block test pattern reduction in on-product test compression system'2015 9,116,205'Test coverage of integrated circuits with test vector input spreading'2015 9,110,135'Chip testing with exclusive OR'2015 9,103,879'Test coverage of integrated circuits with test vector input spreading'2015 9,069,041'Self evaluation of system on a chip with multiple cores'2015 9,032,256'Multi-core processor comparison encoding'2015 9,003,244'Dynamic built-in self-test system'2015 8,898,530'Dynamic built-in self-test system'2014 8,868,975'Testing and operating a multiprocessor chip with processor redundancy'2014 8,856,720'Test coverage of integrated circuits with masking pattern selection'2014 8,762,803'Implementing enhanced pseudo random pattern generators with hierarchical linear feedback shift registers (LFSRs)'2014 8,667,431'Test coverage of integrated circuits with masking pattern selection'2014 8,627,162'Iimplementing enhanced aperture function calibration for logic built in self test (LBIST)'2014 8,516,318'Dynamic scan'2013 8,407,542'Implementing switching factor reduction in LBIST'2013 8,365,006'Preventing circumvention of function disablement in an information handling system'2013 7,949,918'Asynchronous communication using standard boundary architecture cells'2011 7,915,929'High-speed leaf clock frequency-divider/splitter'2011 7,890,824'Asynchronous communication apparatus using JTAG test data registers'2011 7,830,195'Self-test design methodology and technique for root-gated clocking structure'2010 7,793,184'Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression'2010 7,472,324'Logic built-in self-test channel skipping during functional scan operations'2008 7,457,187'Design structure for in-system redundant array repair in integrated circuits'2008 7,405,990'Method and apparatus for in-system redundant array repair on integrated circuits'2008 7,397,709'Method and apparatus for in-system redundant array repair on integrated circuits'2008 7,310,278'Method and apparatus for in-system redundant array repair on integrated circuits'2007 7,114,109'Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features'2006 6,807,645'Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failures'2004 6,735,543'Method and apparatus for testing, characterizing and tuning a chip interface'2004 6,711,706'Method and apparatus for elastic shorts testing, a hardware-assisted wire test mechanism'2004 6,448,835'High-speed leaf splitter for clock gating'2002 6,195,775'Boundary scan latch configuration for generalized scan designs'2001 6,158,032'Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof'2000 6,115,763'Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit'2000 5,717,701'Apparatus and method for testing interconnections between semiconductor devices'1998 5,668,816'Method and apparatus for injecting errors into an array built-in self-test'1997 5,663,966'System and method for minimizing simultaneous switching during scan-based testing'1997 5,617,430'Testing system interconnections using dynamic configuration and test generation'1997 4,972,414'Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2021Patents assigned to IBM (75)· patent assignee history

1990–2021Based in Rochester, MN, US· patent location history

2013–2014Patents assigned to DOUSKEY STEVEN M (5)· patent assignee history

2013–2014Patents assigned to FITCH RYAN A (3)· patent assignee history

2013–2014Patents assigned to HAMILTON MICHAEL J (3)· patent assignee history

2013–2014Patents assigned to KAUFER AMANDA R (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	75	1990–2021
DOUSKEY STEVEN Mself	5	2013–2014
FITCH RYAN A	3	2013–2014
HAMILTON MICHAEL J	3	2013–2014
KAUFER AMANDA R	3	2013–2014

Locations

Location	Patents	Span
Rochester, Minnesota, US	77	1990–2021