Inventor
Sau C. Wong
Inventor
Hillsborough, CA, US
Overview
Patents· 105 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores61%
G06FElectric digital data processing7%
H10BElectronic memory devices7%
H03KPulse technique5%
B64CAeroplanes4%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
H10DInorganic electric semiconductor devices4%
G01RMeasuring electric variables3%
H04NPictorial communication, e.g. television2%
H03MCoding1%
PatentTitleYear
10,535,407Adaptive parallel writing to nonvolatile memory cells202010,468,108Programming nonvolatile memory cells using resolution-based and level-based voltage increments201910,468,107Programming nonvolatile memory cells through a series of predetermined threshold voltages20199,576,647'Parallel programming of nonvolatile memory cells'20179,449,682'Reading a multi-bit value from a memory cell'20168,027,196'Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage'20117,808,820'Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage'20107,656,710'Adaptive operations for nonvolatile memories'20107,554,844'Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency'20097,426,138'Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage'20087,397,697'Multi-bit-per-cell flash EEPROM memory with refresh'20087,355,891'Fabricating bi-directional nonvolatile memory cells'20087,349,255'High data rate write process for non-volatile flash memories'20087,298,670'Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency'20077,268,809'Analog buffer memory for high-speed digital image capture'20077,227,779'Contactless bidirectional nonvolatile memory'20077,221,591'Fabricating bi-directional nonvolatile memory cells'20077,170,781'Multi-bit-per-cell flash EEPROM memory with refresh'20077,139,192'Programming of multi-level memory cells on a continuous word line'20067,106,632'Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency'20067,099,188'Bit line reference circuits for binary and multiple-bit-per-cell memories'20067,092,289'Efficient redundancy system for flash memories with uniformly sized blocks'20067,080,192'File storage and erasure in flash memory'20067,079,422'Periodic refresh operations for non-volatile multiple-bit-per-cell memory'20067,061,801'Contactless bidirectional nonvolatile memory'20067,054,193'Non-uniform programming pulse width for writing of multi-bit-per-cell memories'20066,944,058'High data rate write process for non-volatile flash memories'20056,937,520'Nonvolatile semiconductor memory device'20056,914,820'Erasing storage nodes in a bi-directional nonvolatile memory cell'20056,906,951'Bit line reference circuits for binary and multiple-bit-per-cell memories'20056,898,117'Multi-bit-per-cell flash EEPROM memory with refresh'20056,882,567'Parallel programming of multiple-bit-per-cell memory cells on a continuous word line'20056,856,568'Refresh operations that change address mappings in a non-volatile memory'20056,826,084'Accessing individual storage nodes in a bi-directional nonvolatile memory cell'20046,760,068'Correction of corrupted elements in sensors using analog/multi-level non-volatile memory'20046,760,262'Charge pump circuit adjustable in response to an external voltage source'20046,754,128'Non-volatile memory operations that change a mapping between physical and logical addresses when restoring data'20046,747,896'Bi-directional floating gate nonvolatile memory'20046,731,539'Memory with offset bank select cells at opposite ends of buried diffusion lines'20046,662,263'Sectorless flash memory architecture'20036,624,773'Data encryption and signal scrambling using programmable data conversion arrays'20036,614,685'Flash memory array partitioning architectures'20036,606,267'High data rate write process for non-volatile flash memories'20036,594,036'Analog/multi-level memory for digital imaging'20036,570,810'Contactless flash memory with buried diffusion bit/virtual ground lines'20036,558,967'Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units'20036,556,465'Adjustable circuits for analog or multi-level memory'20036,549,456'Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency'20036,532,556'Data management for multi-bit-per-cell memories'20036,522,586'Dynamic refresh that changes the physical storage locations of data in flash memory'20036,498,851'Data encryption and signal scrambling using programmable data conversion arrays'20026,480,422'Contactless flash memory with shared buried diffusion bit line architecture'20026,466,476'Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell'20026,396,744'Flash memory with dynamic refresh'20026,370,075'Charge pump circuit adjustable in response to an external voltage source'20026,363,008'Multi-bit-cell non-volatile memory with maximized data capacity'20026,345,000'Flash memory permitting simultaneous read/write and erase operations in a single memory array'20026,330,185'High bandwidth multi-level flash memory using dummy memory accesses to improve precision when writing or reading a data stream'20016,317,349'Non-volatile content addressable memory'20016,314,025'High data rate write process for non-volatile flash memories'20016,307,776'Multi-bit-per-cell flash EEPROM memory with refresh'20016,285,593'Word-line decoder for multi-bit-per-cell and analog/multi-level memories with improved resolution and signal-to-noise ratio'20016,278,633'High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations'20016,259,627'Read and write operations using constant row line voltage and variable column line load'20016,208,542'Techniques for storing digital data in an analog or multilevel memory'20016,185,119'Analog memory IC with fully differential signal path'20016,184,726'Adjustable level shifter circuits for analog or multilevel memories'20016,169,503'Programmable arrays for data conversions between analog and digital'20016,166,938'Data encoding for content addressable memories'20006,160,739'Non-volatile memories with improved endurance and extended lifetime'20006,157,558'Content addressable memory cell and array architectures having low transistor counts'20006,154,157'Non-linear mapping of threshold voltages for analog/multi-level memory'20006,151,246'Multi-bit-per-cell flash EEPROM memory with refresh'20006,134,141'Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories'20006,134,145'High data rate write process for non-volatile flash memories'20006,058,060'Multi-bit-per-cell and analog/multi-level non-volatile memories with improved resolution and signal-to noise ratio'20006,038,166'High resolution multi-bit-per-cell memory'20005,969,986'High-bandwidth read and write architectures for non-volatile memories'19995,949,716'Look-ahead erase for sequential data storage'19995,943,283'Address scrambling in a semiconductor memory'19995,923,585'Source biasing in non-volatile memory having row-based sectors'19995,909,387'Memory architecture for recording of multiple messages'19995,909,449'Multibit-per-cell non-volatile memory with error detection and correction'19995,896,340'Multiple array architecture for analog or multi-bit-cell memory'19995,818,757'Analog and multi-level memory with reduced program disturb'19985,815,425'Combined digital write and analog rewrite process for non-volatile memory'19985,801,980'Testing of an analog memory using an on-chip digital input/output interface'19985,751,635'Read circuits for analog memory cells'19985,748,533'Read circuit which uses a coarse-to-fine search when reading the threshold voltage of a memory cell'19985,748,534'Feedback loop for reading threshold voltage'19985,745,409'Non-volatile memory with analog and digital interface and storage'19985,694,356'High resolution analog storage EPROM and flash EPROM'19975,687,115'Write circuits for analog memory'19975,682,352'Digital testing of analog memory devices'19975,680,341'Pipelined record and playback for analog non-volatile memory'19975,638,320'High resolution analog storage EPROM and flash EPROM'19974,912,342'Programmable logic device with array blocks with programmable clocking'19904,899,067'Programmable logic devices with spare circuits for use in replacing defective circuits'19904,899,070'Bit line sense amplifier for programmable logic devices'19904,871,930'Programmable logic device with array blocks connected via programmable interconnect'19894,864,161'Multifunction flip-flop-type circuit'19894,774,421'Programmable logic array device using EPROM technology'19884,713,792'Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits'19874,617,479'Programmable logic array device using EPROM technology'19864,000,413'MOS-RAM'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976Based in San Francisco, CA, US· patent location history
1986–1990Patents assigned to ALTERA CORP (8)· patent assignee history
1986–2011Based in Hillsborough, CA, US· patent location history
1998–2000Patents assigned to INVOX TECHNOLOGY (14)· patent assignee history
2000–2009Patents assigned to SANDISK CORP (33)· patent assignee history
2001–2005Patents assigned to MULTI LEVEL MEMORY TECHNOLOGY (20)· patent assignee history
2001Based in Burlingame, CA, US· patent location history
2006–2020Patents assigned to SAMSUNG ELECTRONICS CO LTD (16)· patent assignee history
2010–2020Based in Reno, NV, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK CORP | 33 | 2000–2009 |
| MULTI LEVEL MEMORY TECHNOLOGY | 20 | 2001–2005 |
| SAMSUNG ELECTRONICS CO LTD | 16 | 2006–2020 |
| INVOX TECHNOLOGY | 14 | 1998–2000 |
| ALTERA CORP | 8 | 1986–1990 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsborough, California, US | 96 | 1986–2011 |
| Reno, NV, US | 6 | 2010–2020 |
| Burlingame, California, US | 2 | 2001 |
| San Francisco, California, US | 1 | 1976 |