Inventor
Lin-June Wu
Inventor
Hsinchu, TW
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10DInorganic electric semiconductor devices19%
H01RElectrically-conductive connections12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
H10BElectronic memory devices6%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H04QSelecting2%
PatentTitleYear
8,870,586'Receptacle connector, plug connector and connector assembly thereof with improved locking structure'20148,777,664'Cable connector, receptacle connector and connector assembly thereof with improved contact arrangement'20148,680,635'CMOS image sensor big via bonding pad application for AICu process'20148,502,335'CMOS image sensor big via bonding pad application for AlCu Process'20138,344,471'CMOS image sensor big via bonding pad application for AICu process'20137,794,271'Cable connector assembly with wire management member thereof'20107,618,282'Snap-fit flat cable connector assembly'20097,604,497'Electrical connector with improved latch'20097,435,096'RF connector assembly having improved connecting member'20087,220,650'Sidewall spacer for semiconductor device and fabrication method thereof'20077,142,538'Message-based communication over bus between cards in an electronic module'20067,067,896'Microelectronic fabrication having edge passivated bond pad integrated with option selection device access aperture'20066,717,220'Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant'20046,693,317'Optical sensor by using tunneling diode'20046,667,230'Passivation and planarization process for flip chip packages'20036,635,576'Method of fabricating borderless contact using graded-stair etch stop layers'20036,611,028'Dynamic substrate-coupled electrostatic discharging protection circuit'20036,582,981'Method of using a tunneling diode in optical sensing devices'20036,531,382'Use of a capping layer to reduce particle evolution during sputter pre-clean procedures'20036,479,872'Dynamic substrate-coupled electrostatic discharging protection circuit'20026,468,904'RPO process for selective CoSix formation'20026,465,308'Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant'20026,362,491'Method of overlay measurement in both X and Y directions for photo stitch process'20026,329,717'Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein'20016,297,102'Method of forming a surface implant region on a ROM cell using a PLDD implant'20016,284,557'Optical sensor by using tunneling diode'20016,258,706'Method for fabricating a stress buffered bond pad'20016,251,724'Method to increase the clear ration of capacitor silicon nitride to improve the threshold voltage uniformity'20016,194,275'Method to form a mask ROM device with coding after source and drain implantation'20016,180,964'Low leakage wire bond pad structure for integrated circuits'20016,077,746'Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process'20005,981,347'Multiple thermal annealing method for a metal oxide semiconductor field effect transistor with enhanced hot carrier effect (HCE) resistance'19995,953,601'ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process'19995,942,800'Stress buffered bond pad and method of making'19995,801,090'Method of protecting an alignment mark in a semiconductor manufacturing process with CMP'19985,747,381'Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback'19985,518,959'Method for selectively depositing silicon oxide spacer layers'19965,393,692'Recessed side-wall poly plugged local oxidation'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (31)· patent assignee history
1995–2014Based in Hsinchu, TW· patent location history
2002Based in Shin-Chu, TW· patent location history
2006Based in Sunnyvale, CA, US· patent location history
2008–2010Patents assigned to HON HAI PREC IND CO LTD (4)· patent assignee history
2008–2014Based in Kunshan, CN· patent location history
2009Based in Tu-Cheng, TW· patent location history
2013Patents assigned to LIN YU-TING (2)· patent assignee history
2014Patents assigned to CHENG WEI-YA (2)· patent assignee history
2014Patents assigned to LANTO ELECTRONIC LTD (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 31 | 1995–2014 |
| HON HAI PREC IND CO LTD | 4 | 2008–2010 |
| CHENG WEI-YA | 2 | 2014 |
| LANTO ELECTRONIC LTD | 2 | 2014 |
| LIN YU-TING | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 30 | 1995–2014 |
| Kunshan, CN | 5 | 2008–2014 |
| Tu-Cheng, TW | 1 | 2009 |
| Sunnyvale, California, US | 1 | 2006 |
| Shin-Chu, TW | 1 | 2002 |