Inventor
Godfrey P. D'Souza
Inventor
San Jose, CA, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing52%
H03KPulse technique21%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%
G11CStatic stores10%
PatentTitleYear
9,081,563'Method and apparatus for enhancing scheduling in an advanced microprocessor'20158,806,247'Adaptive power control'20148,566,627'Adaptive power control'20138,516,224'Pipeline replay support for multicycle operations'20138,405,418'High-bandwidth interconnect network for an integrated circuit'20138,209,517'Method and apparatus for enhancing scheduling in an advanced microprocessor'20128,117,423'Pipeline replay support for multicycle operations'20127,944,236'High-bandwidth interconnect network for an integrated circuit'20117,902,862'High-bandwidth interconnect network for an integrated circuit'20117,886,135'Pipeline replay support for unaligned memory operations'20117,685,403'Pipeline replay support for multi-cycle operations'20107,596,708'Adaptive power control'20097,557,605'Heterogeneous configurable integrated circuit'20097,472,033'Apparatus for controlling semiconductor chip characteristics'20087,134,001'Pipeline replay support for unaligned memory operations'20067,100,061'Adaptive power control'20067,089,404'Method and apparatus for enhancing scheduling in an advanced microprocessor'20066,728,865'Pipeline replay support for unaligned memory operations'20046,604,188'Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction'20036,571,316'Cache memory array for multiple address spaces'20036,513,110'Check instruction and method'20036,011,908'Gated store buffer for an advanced microprocessor'20005,811,992'Dynamic clocked inverter latch with reduced charged leakage and reduced body effect'19985,764,550'Arithmetic logic unit with improved critical path performance'19985,606,270'Dynamic clocked inverter latch with reduced charge leakage'19975,583,821'Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage'19965,568,429'Low power data latch with overdriven clock signals'19965,566,120'Apparatus and method for controlling transistor current leakage'19965,557,581'Logic and memory circuit with reduced input-to-output signal propagation delay'19965,546,022'Static logic circuit with improved output signal levels'19965,483,181'Dynamic logic circuit with reduced charge leakage'19965,471,421'Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage'19955,180,937'Delay compensator and monitor circuit having timing generator and sequencer'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2009Based in Santa Clara, CA, US· patent location history
1995–1998Patents assigned to SUN MICROSYSTEMS INC (10)· patent assignee history
1996–2015Based in San Jose, CA, US· patent location history
2000–2008Patents assigned to TRANSMETA CORP (9)· patent assignee history
2009–2015Patents assigned to D SOUZA GODFREY P (5)· patent assignee history
2010–2013Patents assigned to COON BRETT (4)· patent assignee history
2010–2013Patents assigned to D SOUZA GODFREY (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SUN MICROSYSTEMS INC | 10 | 1995–1998 |
| TRANSMETA CORP | 9 | 2000–2008 |
| D SOUZA GODFREY Pself | 5 | 2009–2015 |
| COON BRETT | 4 | 2010–2013 |
| D SOUZA GODFREYself | 4 | 2010–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 25 | 1996–2015 |
| Santa Clara, California, US | 8 | 1993–2009 |