Inventor
ROBERT M. WALKER
Inventor
US
Overview
Patents· 68 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing74%
G11CStatic stores15%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
H04LTransmission of digital information, e.g. telegraphic communication3%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%
PatentTitleYear
12,596,500Bloom filter integration into a controller202612,411,625Port arbitration202512,405,906Combining read requests having spatial locality202512,394,468Row hammer mitigation using hierarchical detectors202512,386,559Access tracking in memory202512,259,829Memory having internal processors and data communication methods in memory202512,230,311Aliased row hammer detector202512,216,586Dynamically sized redundant write buffer with sector-based tracking202512,210,460Data temperature associated with TLB flush request202512,182,413Area-optimized row hammer mitigation202412,153,796Non-deterministic memory protocol202412,153,832Memory searching component202412,124,741Memory module interfaces202412,112,786Command scheduling component for memory202412,093,565Memory protocol202412,067,270Memory device security and row hammer mitigation202412,056,375Port arbitration202411,947,796Memory protocol202411,914,530Memory having internal processors and data communication methods in memory202411,899,591Dynamically sized redundant write buffer with sector-based tracking202411,893,279Access tracking in memory202411,886,348Interleaved cache prefetching202411,853,605Database persistence202311,853,578Systems, devices, and methods for data migration202311,853,224Cache filter202311,842,059Memory sub-system address mapping202311,829,636Cold data identification202311,822,790Cache line data202311,809,332Prefetch data associated with TLB fill requests202311,809,710Outstanding transaction monitoring for memory sub-systems202311,782,626Systems, devices, techniques, and methods for data migration202311,782,851Dynamic queue depth adjustment202311,755,514Transaction identification202311,740,797Non-deterministic memory protocol202311,734,071Memory sub-system tier allocation202311,709,613Data migration for memory operation202311,704,260Memory controller202311,704,247Enhanced duplicate write data tracking for cache memory202311,687,283Memory module interfaces202311,675,705Eviction of a cache line based on a modification of a sector of the cache line202311,656,995Dynamic access granularity in a cache media202311,599,466Sector-based tracking for a page cache202311,599,472Interleaved cache prefetching202311,593,027Command selection policy with read priority202311,586,566Memory protocol with command priority202311,550,725Dynamically sized redundant write buffer with sector-based tracking202311,543,978Credit-based scheduling of memory commands202311,526,306Command scheduling in a memory subsystem according to a selected scheduling ordering202211,494,119Memory searching component202211,442,648Data migration dynamic random access memory202211,422,705Non-deterministic memory protocol202211,403,240Memory having internal processors and data communication methods in memory202211,403,035Memory module including a controller and interfaces for communicating with a host and another memory module202211,397,683Low latency cache for non-volatile memory in a hybrid DIMM202211,366,762Cache filter202211,340,787Memory protocol202211,314,643Enhanced duplicate write data tracking for cache memory202211,301,380Sector-based tracking for a page cache202211,301,383Managing processing of memory commands in a memory subsystem with a high latency backing store202211,288,214Command selection policy202211,256,437Data migration for memory operation202211,243,889Cache architecture for comparing data on a single page202211,237,995Transaction identification202211,226,770Memory protocol202211,188,234Cache line data202111,182,090Systems, devices, and methods for data migration202111,175,859Managing memory commands in a memory subsystem by adjusting a maximum number of low priority commands in a DRAM controller202111,163,473Systems, devices, techniques, and methods for data migration2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to MICRON TECHNOLOGY INC (62)· patent assignee history
2021–2026Based in US· patent location history
2024–2025Patents assigned to LODESTAR LICENSING GROUP LLC (5)· patent assignee history
2026Patents assigned to MICRON TECH INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 62 | 2021–2025 |
| LODESTAR LICENSING GROUP LLC | 5 | 2024–2025 |
| MICRON TECH INC | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 68 | 2021–2026 |