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Inventor

Gregory S. Mathews

Inventor
Santa Clara, CA, US

Overview

48→
Patents
1992–2021
Patent span
Physics
Primary field (CPC G)

Patents· 48 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing69%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
H04LTransmission of digital information, e.g. telegraphic communication10%
G11CStatic stores2%
H03KPulse technique2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
H04QSelecting2%
PatentTitleYear
10,901,617Memory access scheduling using category arbitration202110,838,884Memory access quality-of-service reallocation202010,817,219Memory access scheduling using a linked list202010,783,104Memory request management system202010,777,252System and method for performing per-bank memory refresh202010,678,478Ordering memory requests based on access efficiency202010,621,115System and method for communication link management in a credit-based system202010,545,701Memory arbitration techniques based on latency tolerance202010,437,758Memory request management system201910,175,905Systems and methods for dynamically switching memory performance states20197,876,693'Testing and error recovery across multiple switching fabrics'20117,801,045'Hierarchical rate limiting with proportional limiting'20107,733,888'Pointer allocation by prime numbers'20107,525,917'Flow control in a distributed scalable, shared memory switching fabric system'20097,394,822'Using reassembly queue sets for packet reassembly'20087,349,336'Random early drop with per hop behavior biasing'20087,242,691'Optimal load balancing across multiple switching fabrics'20076,725,339'Processing ordered data requests to a memory'20046,687,790'Single bank associative cache'20046,681,317'Method and apparatus to provide advanced load ordering'20046,678,815'Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end'20046,658,559'Method and apparatus for advancing load operations'20036,625,715'System and method for translation buffer accommodating multiple page sizes'20036,567,952'Method and apparatus for set associative cache tag error detection'20036,560,689'TLB using region ID prevalidation'20036,542,966'Method and apparatus for managing temporal and non-temporal data in a single cache structure'20036,427,191'High performance fully dual-ported, pipelined cache design'20026,418,521'Hierarchical fully-associative-translation lookaside buffer structure'20026,405,233'Unaligned semaphore adder'20026,381,678'Processing ordered data requests to a memory'20026,282,636'Decentralized exception processing system'20016,275,901'Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array'20016,272,597'Dual-ported, pipelined, two level cache system'20016,233,652'Translation lookaside buffer for multiple page sizes'20016,223,263'Method and apparatus for locking and unlocking a memory region'20016,134,636'Method and apparatus for storing data in a memory array'20006,105,115'Method and apparatus for managing a memory array'20005,956,752'Method and apparatus for accessing a cache using index prediction'19995,802,577'Multi-processing cache coherency protocol on a local bus'19985,634,131'Method and apparatus for independently stopping and restarting functional units'19975,481,697'An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies'19965,469,544'Central processing unit address pipelining'19955,398,244'Method and apparatus for reduced latency in hold bus cycles'19955,392,437'Method and apparatus for independently stopping and restarting functional units'19955,359,723'Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only'19945,278,964'Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache'19945,276,888'Computer system with interrupts transparent to its operating system and application programs'19945,175,853'Transparent system interrupt'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2004Patents assigned to INTEL CORP (31)· patent assignee history
1992–2004Based in Cupertino, CA, US· patent location history
1995–2011Based in Santa Clara, CA, US· patent location history
1995–1997Based in Boca Raton, FL, US· patent location history
2007–2008Patents assigned to LUCENT TECHNOLOGIES INC (3)· patent assignee history
2009Patents assigned to ACATEL LUCENT USA INC (1)· patent assignee history
2010–2011Patents assigned to ALCATEL LUCENT USA INC (2)· patent assignee history
2010–2021Based in Saratoga, CA, US· patent location history
2019–2021Patents assigned to APPLE INC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP311992–2004
APPLE INC102019–2021
LUCENT TECHNOLOGIES INC32007–2008
ALCATEL LUCENT USA INC22010–2011
ACATEL LUCENT USA INC12009
Locations
LocationPatentsSpan
Santa Clara, California, US271995–2011
Saratoga, California, US112010–2021
Cupertino, California, US71992–2004
Boca Raton, Florida, US31995–1997