LexDanaLexDanabeta
Inventor

Adrian E. Ong

Inventor
Pleasanton, CA, US

Overview

120→
Patents
1994–2021
Patent span
Physics
Primary field (CPC G)

Patents· 120 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores50%
G01RMeasuring electric variables17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G06FElectric digital data processing7%
H01LSemiconductor devices4%
H10BElectronic memory devices4%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses1%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
Y10TTechnical subjects covered by former us classification1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
11,009,548Testing fuse configurations in semiconductor devices202110,867,691Controller to detect malfunctioning address of memory device202010,854,255Vertical selector stt-MRAM architecture202010,840,298Vertical selector STT-MRAM architecture202010,818,334Ferroelectric memory array with variable plate-line architecture202010,803,918Ferroelectric memory array with hierarchical plate-line architecture202010,446,256Controller to detect malfunctioning address of memory device201910,302,696Testing fuse configurations in semiconductor devices201910,114,073Integrated circuit testing201810,032,500Memory disturb recovery scheme for cross-point memory arrays201810,008,291Controller to detect malfunctioning address of memory device20189,899,312'Isolating electric paths in semiconductor device packages'20189,679,664'Method and system for providing a smart memory architecture'20179,659,671'Controller to detect malfunctioning address of memory device'20179,653,151'Memory array having segmented row addressed page registers'20179,607,681'Memory device that supports multiple memory configurations'20179,568,544'Testing fuse configurations in semiconductor devices'20179,378,849'Controller to detect malfunctioning address of memory device'20169,269,460'Controller to detect malfunctioning address of memory device'20169,141,473'Parallel memory error detection and correction'20159,129,712'Programmable memory repair scheme'20159,116,210'Integrated circuit testing module including signal shaping interface'20159,111,625'Adaptive dual voltage write driver with dummy resistive path tracking'20159,099,181'Non-volatile static ram cell circuit and timing method'20159,076,541'Architecture for magnetic memories including magnetic tunneling junctions using spin-orbit interaction based switching'20159,069,719'Method and system for providing a smart memory architecture'20159,001,607'Method and design for high performance non-volatile memory'20158,908,428'Voltage assisted STT-MRAM writing scheme'20148,750,018'Sense amplifier circuitry for resistive type memory'20148,723,557'Multi-supply symmetric driver circuit and timing method'20148,717,052'Testing fuse configurations in semiconductor devices'20148,711,646'Architecture, system and method for testing resistive type memory'20148,670,283'Controller to detect malfunctioning address of memory device'20148,625,339'Multi-cell per memory-bit circuit and method'20148,456,926'Memory write error correction circuit'20138,446,788'Programmable memory repair scheme'20138,411,497'Method and system for providing a magnetic field aligned spin transfer torque random access memory'20138,385,106'Method and system for providing a hierarchical data path for spin transfer torque random access memory'20138,315,090'Pseudo page mode memory architecture and method'20128,286,046'Integrated circuit testing module including signal shaping interface'20128,195,992'Processor-memory unit for use in system-in-package and system-in-module devices'20128,166,361'Integrated circuit testing module configured for set-up and hold time testing'20128,077,508'Dynamic multistate memory write driver'20118,077,501'Differential read and write architecture'20118,063,650'Testing fuse configurations in semiconductor devices'20118,001,439'Integrated circuit testing module including signal shaping interface'20117,991,572'Delay lock loop delay adjusting method and apparatus'20117,945,824'Processor-memory unit for use in system-in-package and system-in-module devices'20117,779,311'Testing and recovery in a multilayer device'20107,768,847'Programmable memory repair scheme'20107,706,998'Delay lock loop delay adjusting method and apparatus'20107,673,193'Processor-memory unit for use in system-in-package and system-in-module devices'20107,593,271'Memory device including multiplexed inputs'20097,466,603'Memory accessing circuit system'20087,466,160'Shared memory bus architecture for system with processor and memory units'20087,446,551'Integrated circuit testing module including address generator'20087,443,188'Electronic device having an interface supported testing mode'20087,444,575'Architecture and method for testing of an integrated circuit device'20087,404,117'Component testing and recovery'20087,370,256'Integrated circuit testing module including data compression'20087,365,557'Integrated circuit testing module including data generator'20087,313,740'Internally generating patterns for testing in an integrated circuit device'20077,309,999'Electronic device having an interface supported testing mode'20077,310,000'Integrated circuit testing module including command driver'20077,307,442'Integrated circuit test array including test module'20077,269,524'Delay lock loop delay adjusting method and apparatus'20077,265,570'Integrated circuit testing module'20077,259,582'Bonding pads for testing of a semiconductor device'20077,245,141'Shared bond pad for testing a memory within a packaged semiconductor device'20077,240,254'Multiple power levels for a chip within a multi-chip semiconductor package'20077,157,940'System and methods for a high-speed dynamic data bus'20077,139,945'Chip testing within a multi-chip semiconductor package'20067,133,798'Monitoring signals between two integrated circuit devices within a single package'20067,103,815'Testing of integrated circuit devices'20067,061,263'Layout and use of bond pads and probe pads for testing of integrated circuits devices'20067,006,940'Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip'20066,996,652'High-speed segmented data bus architecture'20066,983,404'Method and apparatus for checking the resistance of programmable elements'20066,882,171'Bonding pads for testing of a semiconductor device'20056,812,726'Entering test mode and accessing of a packaged semiconductor device'20046,754,866'Testing of integrated circuit devices'20046,732,304'Chip testing within a multi-chip semiconductor package'20046,657,914'Configurable addressing for multiple chips in a package'20036,365,421'Method and apparatus for storage of test results within an integrated circuit'20026,208,568'Circuit for cancelling and replacing redundant elements'20016,194,738'Method and apparatus for storage of test results within an integrated circuit'20016,188,594'Reduced-pitch 6-transistor NMOS content-addressable-memory cell'20016,185,705'Method and apparatus for checking the resistance of programmable elements'20016,166,976'Multiple equilibration circuits for a single bit line'20006,154,410'Method and apparatus for reducing antifuse programming time'20006,154,386'Memory device having a wide data path'20006,104,645'High speed global row redundancy system'2000RE036821'Wordline driver circuit having a directly gated pull-down device'20006,097,647'Efficient method for obtaining usable parts from a partially good memory integrated circuit'20006,078,513'NMOS dynamic content-addressable-memory CAM cell with self-booting pass transistors and local row and column select'20006,033,945'Multiple equilibration circuits for a single bit line'20006,031,784'Hierarchical decoding of a memory device'20005,999,480'Dynamic random-access memory having a hierarchical data path'19995,970,020'Controlling the set up of a memory address'19995,970,008'Efficient method for obtaining usable parts from a partially good memory integrated circuit'19995,919,269'Supervoltage detection circuit having a multi-level reference voltage'19995,912,579'Circuit for cancelling and replacing redundant elements'19995,901,105'Dynamic random access memory having decoding circuitry for partial memory blocks'19995,850,368'Burst EDO memory address counter'19985,838,620'Circuit for cancelling and replacing redundant elements'19985,798,970'Memory device output buffer'19985,761,145'Efficient method for obtaining usable parts from a partially good memory integrated circuit'19985,745,499'Supervoltage detection circuit having a multi-level reference voltage'1998RE035750'Wordline driver circuit having an automatic precharge circuit'19985,706,238'Self current limiting antifuse circuit'19985,677,884'Circuit for cancelling and replacing redundant elements'19975,675,549'Burst EDO memory device address counter'19975,631,862'Self current limiting antifuse circuit'19975,614,859'Two stage voltage level translator'19975,602,783'Memory device output buffer'19975,528,539'High speed global row redundancy system'19965,488,583'Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits'19965,465,232'Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory'19955,311,481'Wordline driver circuit having a directly gated pull-down device'19945,293,342'Wordline driver circuit having an automatic precharge circuit'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2006Patents assigned to MICRON TECHNOLOGY INC (26)· patent assignee history
1994–2001Based in Boise, ID, US· patent location history
1997–2012Based in San Jose, CA, US· patent location history
1997–1998Based in Santa Clara, CA, US· patent location history
1999–2021Based in Pleasanton, CA, US· patent location history
2003–2008Patents assigned to INAPAC TECHNOLOGY INC (29)· patent assignee history
2009–2021Patents assigned to RAMBUS INC (28)· patent assignee history
2011–2018Patents assigned to ONG ADRIAN E (22)· patent assignee history
2011–2015Patents assigned to GRANDIS INC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INAPAC TECHNOLOGY INC292003–2008
RAMBUS INC282009–2021
MICRON TECHNOLOGY INC261994–2006
ONG ADRIAN Eself222011–2018
GRANDIS INC92011–2015
Locations
LocationPatentsSpan
Pleasanton, California, US861999–2021
Boise, ID, US171994–2001
San Jose, California, US151997–2012
Santa Clara, California, US21997–1998