Inventor

Bradley A. Sharpe-Geisler

Inventor

San Jose, CA, US

Overview

1988–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 97 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique56%

G06FElectric digital data processing9%

H10DInorganic electric semiconductor devices6%

G11CStatic stores6%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%

G05FSystems for regulating electric or magnetic variables4%

H04LTransmission of digital information, e.g. telegraphic communication3%

H10BElectronic memory devices2%

G01RMeasuring electric variables2%

H03MCoding2%

PatentTitleYear

10,764,026Acoustic gesture recognition systems and methods2020 10,466,738Low-speed bus time stamp methods and circuitry2019 10,326,627Clock recovery and data recovery for programmable logic devices2019 10,148,472Clock recovery and data recovery for programmable logic devices2018 RE039510'FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections'2007 7,028,281'FPGA with register-intensive architecture'2006 7,000,212'Hierarchical general interconnect architecture for high density FPGA\'S'2006 6,919,736'Field programmable gate array having embedded memory with configurable depth and width'2005 6,870,391'Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility'2005 6,798,244'Output buffer with overvoltage protection'2004 6,760,209'Electrostatic discharge protection circuit'2004 6,753,696'Programmable optimized-distribution logic allocator for a high-density complex PLD'2004 6,725,442'Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device'2004 6,720,755'Band gap reference circuit'2004 6,714,043'Output buffer having programmable drive current and output voltage limits'2004 6,714,048'Input buffer with voltage clamping for compatibility'2004 6,657,458'Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility'2003 6,621,298'Variable grain architecture for FPGA integrated circuits'2003 6,590,415'Methods for configuring FPGA\'s having variable grain components for providing time-shared access to interconnect resources'2003 6,531,890'Programmable optimized-distribution logic allocator for a high-density complex PLD'2003 6,526,558'Methods for configuring FPGA\'s having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources'2003 6,470,485'Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device'2002 6,380,759'Variable grain architecture for FPGA integrated circuits'2002 6,359,466'Circuitry to provide fast carry'2002 6,353,352'Clock tree topology'2002 6,351,157'Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5 volt) semiconductor process'2002 6,326,808'Inversion of product term line before or logic in a programmable logic device (PLD)'2001 6,292,930'Methods for configuring FPGA\'s having variable grain blocks and shared logic for providing time-shared access to interconnect resources'2001 6,275,064'Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits'2001 6,249,144'Methods for configuring FPGA\'s having variable grain components for providing time-shared access to interconnect resources'2001 6,228,696'Semiconductor-oxide-semiconductor capacitor formed in integrated circuit'2001 6,218,857'Variable sized line driving amplifiers for input/output blocks (IOBs) in FPGA integrated circuits'2001 6,216,257'FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks'2001 6,211,695'FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections'2001 6,204,686'Methods for configuring FPGA\'s having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources'2001 6,191,612'Enhanced I/O control flexibility for generating control signals'2001 6,181,163'FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals'2001 6,175,266'Operational amplifier with CMOS transistors made using 2.5 volt process transistors'2001 6,169,432'High voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt process'2001 6,163,168'Efficient interconnect network for use in FPGA device having variable grain architecture'2000 6,163,175'High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device'2000 6,154,051'Tileable and compact layout for super variable grain blocks within FPGA device'2000 6,150,842'Variable grain architecture for FPGA integrated circuits'2000 6,130,551'Synthesis-friendly FPGA architecture with variable length and variable timing interconnect'2000 6,127,843'Dual port SRAM memory for run time use in FPGA integrated circuits'2000 6,124,730'Methods for configuring FPGA\'s having variable grain components for providing time-shared access to interconnect resources'2000 6,124,733'Input buffer providing virtual hysteresis'2000 6,107,823'Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits'2000 6,100,715'Methods for configuring FPGA\'s having variable grain blocks and logic for providing time-shared access to interconnect resources'2000 6,097,664'Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan'2000 6,097,212'Variable grain architecture for FPGA integrated circuits'2000 6,091,595'Electrostatic discharge (ESD) protection for NMOS pull up transistors of a 5.0 volt compatible output buffer using 2.5 volt process transistors'2000 6,081,473'FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode'2000 6,072,351'Output buffer for making a 5.0 volt compatible input/output in a 2.5 volt semiconductor process'2000 6,043,969'Ballast resistors with parallel stacked NMOS transistors used to prevent secondary breakdown during ESD with 2.5 volt process transistors'2000 6,034,544'Programmable input/output block (IOB) in FPGA integrated circuits'2000 6,031,365'Band gap reference using a low voltage power supply'2000 6,028,758'Electrostatic discharge (ESD) protection for a 5.0 volt compatible input/output (I/O) in a 2.5 volt semiconductor process'2000 5,990,702'Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits'1999 5,986,480'Multiple input zero power AND/NOR gate for use in a field programmable gate array (FPGA)'1999 5,982,193'Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits'1999 5,912,550'Power converter with 2.5 volt semiconductor process components'1999 5,905,385'Memory bits used to couple look up table inputs to facilitate increased availability to routing resources particularly for variable sized look up tables for a field programmable gate array (FPGA)'1999 5,844,912'Fast verify for CMOS memory cells'1998 5,818,254'Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices'1998 5,811,987'Block clock and initialization circuit for a complex high density PLD'1998 5,808,942'Field programmable gate array (FPGA) having an improved configuration memory and look up table'1998 5,796,295'Reference for CMOS memory cell having PMOS and NMOS transistors with a common floating gate'1998 5,789,939'Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device'1998 5,781,030'Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD'1998 5,760,609'Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device'1998 5,751,164'Programmable logic device with multi-level power control'1998 5,739,713'Deconvolution input buffer compensating for capacitance of a switch matrix of a high density programmable logic device'1998 5,736,888'Capacitance elimination circuit which provides current to a node in a circuit to eliminate the effect of parasitic capacitance at the node'1998 5,723,984'Field programmable gate array (FPGA) with interconnect encoding'1998 5,719,516'Lock generator circuit for use with a dual edge register that provides a separate enable for each use of an input clock signal'1998 5,668,488'Input buffer for a high density programmable logic device'1997 5,646,901'CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors'1997 5,638,018'P-type flip-flop'1997 5,596,524'CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase'1997 5,594,687'Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase'1997 5,589,782'Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide multiple functions'1996 5,583,451'Polarity control circuit which may be used with a ground bounce limiting buffer'1996 5,570,046'Lead frame with noisy and quiet V.sub.SS and V.sub.DD leads'1996 5,568,066'Sense amplifier and or gate for a high density programmable logic device'1996 5,521,529'Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation'1996 5,495,195'Output buffer for a high density programmable logic device'1996 5,491,433'Cascode array cell partitioning for a sense amplifier of a programmable logic device'1996 5,469,088'Cascade array cell partitioning for a sense amplifier of a programmable logic device'1995 5,457,404'Zero-power OR gate'1995 5,438,277'Ground bounce isolated output buffer'1995 5,410,268'Latching zero-power sense amplifier with cascode'1995 5,406,139'Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching'1995 5,084,404'Gate array structure and process to allow optioning at second metal mask only'1992 5,023,701'Gate array structure and process to allow optioning at second metal mask only'1991 4,855,711'Impact detection apparatus'1989 4,740,485'Method for forming a fuse'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988Patents assigned to MONOLITHIC MEMORIES INC (1)· patent assignee history

1988–2020Based in San Jose, CA, US· patent location history

1989Patents assigned to SENSOR SCIENCE (1)· patent assignee history

1991–2000Patents assigned to ADVANCED MICRO DEVICES INC (36)· patent assignee history

1999–2002Patents assigned to VANTIS CORP (34)· patent assignee history

2000–2020Patents assigned to LATTICE SEMICONDUCTOR CORP (25)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	36	1991–2000
VANTIS CORP	34	1999–2002
LATTICE SEMICONDUCTOR CORP	25	2000–2020
MONOLITHIC MEMORIES INC	1	1988
SENSOR SCIENCE	1	1989

Locations

Location	Patents	Span
San Jose, California, US	97	1988–2020