Inventor
Hsing-Lien Lin
Inventor
Hsinchu, TW
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices14%
H10NElectric solid-state devices not otherwise provided for13%
H10BElectronic memory devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
H10KOrganic electric solid-state devices4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
G11CStatic stores3%
C23CCoating metallic material2%
PatentTitleYear
10,868,247Semiconductor device structure with multiple resistance variable layers202010,818,544Method to enhance electrode adhesion stability202010,818,857Organic photosensitive device with an electron-blocking and hole-transport layer202010,811,600Switching layer scheme to enhance RRAM performance202010,804,464Method of forming memory device with diffusion barrier and capping layer202010,787,360Semiconductor MEMS structure202010,748,967Image sensors with organic photodiodes and methods for forming the same202010,658,581Semiconductor device structure with multiple resistance variable layers202010,622,555Film scheme to improve peeling in chalcogenide based PCRAM202010,505,107Switching layer scheme to enhance RRAM performance201910,497,773Method to improve MIM device performance201910,388,865High yield RRAM cell with optimized film scheme201910,273,142Semiconductor MEMS structure201910,193,065High K scheme to improve retention performance of resistive random access memory (RRAM)201910,176,866Recap layer scheme to enhance RRAM performance201910,170,699RRAM cell bottom electrode formation201910,164,182Switching layer scheme to enhance RRAM performance201810,164,003MIM capacitor and method of forming the same201810,079,257Anti-reflective layer for backside illuminated CMOS image sensors201810,008,546Image sensors with organic photodiodes and methods for forming the same20189,978,938Resistive RAM structure and method of fabrication thereof20189,960,353Method of fabricating an organic photodiode with dual electron blocking layers20189,954,166Embedded memory device with a composite top electrode20189,876,167High yield RRAM cell with optimized film scheme20189,876,184Organic photosensitive device with an electron-blocking and hole-transport layer20189,847,401Semiconductor device and method of forming the same20179,828,234Semiconductor MEMS structure and manufacturing method thereof20179,825,117'MIM/RRAM structure with improved capacitance and reduced leakage current'20179,818,885'Deposited material and method of formation'20179,728,597'Metal-insulator-metal structure and method for forming the same'20179,722,011'Film scheme for MIM device'20179,647,207'Resistive random access memory (RRAM) structure'20179,627,613'Resistive random access memory (RRAM) cell with a composite capping layer'20179,577,191'RRAM cell bottom electrode formation'20179,564,330'Normally-off enhancement-mode MISFET'20179,543,375'MIM/RRAM structure with improved capacitance and reduced leakage current'20179,524,868'Deposited material and method of formation'20169,484,537'Organic photo diode with dual electron blocking layers'20169,450,183'Memory structure having top electrode with protrusion'20169,431,609'Oxide film scheme for RRAM structure'20169,425,240'Image sensors with organic photodiodes and methods for forming the same'20169,425,061'Buffer cap layer to improve MIM structure performance'20169,418,999'MIM capacitors with improved reliability'20169,257,272'Deposited material and method of formation'20169,257,642'Protective sidewall techniques for RRAM'20169,257,497'Metal-insulator-metal (MIM) capacitor techniques'20169,130,026'Crystalline layer for passivation of III-N surface'20158,889,507'MIM capacitors with improved reliability'20148,759,234'Deposited material and method of formation'20147,851,324'Method of forming metal-insulator-metal structure'20107,529,078'Low tunneling current MIM structure and method of manufacturing same'20097,199,001'Method of forming MIM capacitor electrodes'20076,180,503'Passivation layer etching process for memory arrays with fusible links'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001Based in Kaohsiung, TW· patent location history
2007–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (6)· patent assignee history
2007–2020Based in Hsinchu, TW· patent location history
2014Patents assigned to LIN HSING-LIEN (2)· patent assignee history
2014Patents assigned to CHANG LUCY (1)· patent assignee history
2014Patents assigned to CHANG YAO-WEN (1)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (46)· patent assignee history
2018Based in Jinshan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 46 | 2015–2020 |
| TAIWAN SEMICONDUCTOR MFG | 6 | 2007–2016 |
| LIN HSING-LIENself | 2 | 2014 |
| CHANG LUCY | 1 | 2014 |
| CHANG YAO-WEN | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 51 | 2007–2020 |
| Jinshan, TW | 1 | 2018 |
| Kaohsiung, TW | 1 | 2001 |