Inventor
Jeewika Ranaweera
Inventor
San Jose, CA, US
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1057%
H01LSemiconductor devices14%
H10DInorganic electric semiconductor devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
PatentTitleYear
10,593,631Warping reduction in silicon wafers20206,767,769'Metal-to-metal antifuse employing carbon-containing antifuse material'20046,713,369'Antifuse incorporating tantalum nitride barrier layer'20046,603,142'Antifuse incorporating tantalum nitride barrier layer'20036,034,896'Method of fabricating a fast programmable flash E.sup.2 PROM cell'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000Patents assigned to UNIV TORONTO (1)· patent assignee history
2000Based in Ontario, CA· patent location history
2003–2004Patents assigned to ACTEL CORP (3)· patent assignee history
2003–2020Based in San Jose, CA, US· patent location history
2020Patents assigned to ORACLE INT CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ACTEL CORP | 3 | 2003–2004 |
| ORACLE INT CORP | 1 | 2020 |
| UNIV TORONTO | 1 | 2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 4 | 2003–2020 |
| Ontario, CA | 1 | 2000 |