Inventor
MIKE MACPHERSON
Inventor
US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing31%
G06TImage data processing or generation, in general28%
G06NComputing arrangements based on specific computational models23%
H03MCoding14%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
12,561,276Systems and methods for updating memory side caches in a multi-GPU configuration202612,561,277Memory controller management techniques for managing data transfer for memory access operations202612,554,674Multi-tile memory management202612,399,685Systolic array having support for output sparsity202512,373,912Prefetch status notification for memory prefetching202512,346,694Register file for systolic array202512,321,310Implicit fence for write messages202512,293,431Sparse optimizations for a matrix accelerator architecture202512,254,526On chip dense memory for temporal buffering202512,242,414Data initialization techniques202512,229,867Graphics architecture including a neural network pipeline202512,210,477Systems and methods for improving cache efficiency and utilization202512,204,487Graphics processor data access and sharing202512,198,222Architecture for block sparse operations on a systolic array202512,182,062Multi-tile memory management202412,153,541Cache structure and utilization202412,141,094Systolic disaggregation within a matrix accelerator architecture202412,117,962Scalar core integration202412,099,461Multi-tile memory management202412,093,210Compression techniques202412,079,155Graphics processor operation scheduling for deterministic latency202412,066,975Cache structure and utilization202412,001,944Tool for facilitating efficiency in machine learning202411,995,029Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration202411,934,342Assistance for hardware prefetch in cache access202411,899,614Instruction based control of memory attributes202411,892,950Data prefetching for graphics data processing202411,861,759Memory prefetching in multiple GPU environment202411,842,423Dot product operations on sparse matrix elements202311,809,905Local memory sharing between kernels202311,762,804Scalar core integration202311,676,322Graphics architecture including a neural network pipeline202311,676,239Sparse optimizations for a matrix accelerator architecture202311,620,256Systems and methods for improving cache efficiency and utilization202311,410,024Tool for facilitating efficiency in machine learning202211,409,693Scalar core integration202211,409,658Data prefetching for graphics data processing202211,232,533Memory prefetching in multiple GPU environment202211,151,769Graphics architecture including a neural network pipeline2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (39)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 39 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 39 | 2021–2026 |