Inventor
HONG WAN NG
Inventor
SG
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H05KPrinted circuits7%
H10DInorganic electric semiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H10BElectronic memory devices3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
C09JAdhesives1%
G06FElectric digital data processing1%
H01GCapacitors1%
PatentTitleYear
12,593,706Multi-chip package with enhanced conductive layer adhesion202612,588,527Dielectric interposer with electrical-connection cut-in202612,581,976Wire bonding directly on exposed conductive vias and interconnects and related systems and methods202612,564,096Nested semiconductor assemblies and methods for making the same202612,532,781Stacked capacitors for semiconductor devices and associated systems and methods202612,525,521Package substrate for a semiconductor device202612,512,437Semiconductor device assemblies with balanced wires, and associated methods202512,476,216Wire bonding for stacked memory dies202512,463,140Flexible interposer for semiconductor dies202512,444,709Overlapping die stacks for NAND package architecture202512,438,113Conductive adhesive assembly for semiconductor die attachment202512,432,859Surface mount device bonded to an inner layer of a multi-layer substrate202512,431,418Three dimensional semiconductor trace length matching and associated systems and methods202512,412,811Split via structure for semiconductor device packaging202512,374,612Microelectronic device packages and related methods and systems202512,368,113Methods and apparatus for using spacer-on-spacer design for solder joint reliability improvement in semiconductor devices202512,362,319Cross stack bridge bonding devices and associated methods202512,362,247Semiconductor devices with flexible spacer including a support structure and methods of making the same202512,362,255Apparatus including direct-contact heat paths and methods of manufacturing the same202512,354,939Multi-role semiconductor device substrates, semiconductor device assemblies employing the same, and methods for forming the same202512,315,769Build-up package for integrated circuit devices, and methods of making same202512,293,992Semiconductor assemblies with systems and methods for managing high die stack structures202512,243,807Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods202512,237,301Through stack bridge bonding devices and associated methods202512,148,736Three-dimensional bonding scheme and associated systems and methods202412,080,616Reinforced semiconductor device packaging and associated systems and methods202411,942,460Systems and methods for reducing the size of a semiconductor assembly202411,929,351Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer202411,908,833Overlapping die stacks for nand package architecture202411,894,289Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods202411,855,065Stacked semiconductor die assemblies with support members and associated systems and methods202311,824,044Stacked semiconductor die assemblies with die support members and associated systems and methods202311,723,150Surface mount device bonded to an inner layer of a multi-layer substrate202311,710,722Semiconductor assemblies with systems and methods for managing high die stack structures202311,658,154Memory devices with controllers under memory packages and associated systems and methods202311,562,987Semiconductor devices with multiple substrates and die stacks202311,527,459Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods202211,367,667Build-up package for integrated circuit devices, and methods of making same202211,309,281Overlapping die stacks for NAND package architecture202211,282,811Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to MICRON TECHNOLOGY INC (40)· patent assignee history
2022–2026Based in SG· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 40 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| SG | 40 | 2022–2026 |