Inventor
Pin-Shyne Chin
Inventor
Hsinchu, TW
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices33%
H10DInorganic electric semiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests17%
PatentTitleYear
7,244,641'Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device'20077,183,150'Resist protect oxide structure of sub-micron salicide process'20077,064,371'Low leakage one transistor static random access memory'20066,852,589'Method to modify 0.25 μm 1T-RAM by extra resist protect oxide (RPO) blocking'20056,849,485'Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device'20056,815,274'Resist protect oxide structure of sub-micron salicide process'20046,790,724'Low leakage one transistor static random access memory'20046,528,422'Method to modify 0.25m 1T-RAM by extra resist protect oxide (RPO) blocking'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2007Patents assigned to TAIWAN SEMICONDUCTOR MFG (8)· patent assignee history
2003–2007Based in Hsinchu, TW· patent location history
2005–2007Based in Shin-Chu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 8 | 2003–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 6 | 2003–2007 |
| Shin-Chu, TW | 2 | 2005–2007 |