Inventor
Yeow Kheng Lim
Inventor
Singapore, SG
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1052%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10DInorganic electric semiconductor devices13%
H01LSemiconductor devices7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
PatentTitleYear
9,318,378'Slot designs in wide metal lines'20168,957,523'Dielectric posts in metal layers'20158,860,185'Crack-arresting structure for through-silicon vias'20148,766,454'Integrated circuit with self-aligned line and via'20148,759,947'Back-side MOM/MIM devices'20148,716,856'Device with integrated power supply'20148,466,062'TSV backside processing using copper damascene interconnect technology'20138,358,007'Integrated circuit system employing low-k dielectrics and method of manufacture thereof'20137,790,617'Formation of metal silicide layer over copper interconnect for reliability enhancement'20107,372,156'Method to fabricate aligned dual damascene openings'20087,253,097'Integrated circuit system using dual damascene process'20077,119,010'Integrated circuit with self-aligned line and via and manufacturing method therefor'20066,967,156'Method to fabricate aligned dual damascene openings'20056,849,928'Dual silicon-on-insulator device wafer die'20056,780,691'Method to fabricate elevated source/drain transistor with large area for silicidation'20046,613,652'Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance'20036,558,994'Dual silicon-on-insulator device wafer die'20036,518,133'Method for fabricating a small dimensional gate with elevated source/drain structures'20036,472,697'Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application'20026,468,880'Method for fabricating complementary silicon on insulator devices using wafer bonding'20026,432,797'Simplified method to reduce or eliminate STI oxide divots'20026,399,471'Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application'20026,380,084'Method to form high performance copper damascene interconnects by de-coupling via and metal line filling'20026,355,563'Versatile copper-wiring layout design with low-k dielectric integration'20026,319,767'Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2010Patents assigned to CHARTERED SEMICONDUCTOR MFG (15)· patent assignee history
2001–2016Based in Singapore, SG· patent location history
2013–2016Patents assigned to GLOBALFOUNDRIES SG PTE LTD (8)· patent assignee history
2013–2016Patents assigned to LIM YEOW KHENG (7)· patent assignee history
2013–2014Patents assigned to TAN JUAN BOON (5)· patent assignee history
2014Patents assigned to GONG SHUNQIANG (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CHARTERED SEMICONDUCTOR MFG | 15 | 2001–2010 |
| GLOBALFOUNDRIES SG PTE LTD | 8 | 2013–2016 |
| LIM YEOW KHENGself | 7 | 2013–2016 |
| TAN JUAN BOON | 5 | 2013–2014 |
| GONG SHUNQIANG | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 25 | 2001–2016 |