Inventor
Jacob Riseman
Inventor
Poughkeepsie, NY, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests15%
G11CStatic stores5%
H10BElectronic memory devices5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
4,944,836'Chem-mech polishing method for producing coplanar metal/insulator films on a substrate'19904,729,006'Sidewall spacers for CMOS circuit stress relief/isolation and method for making'19884,712,125'Structure for contacting a narrow width PN junction region'19874,689,113'Process for forming planar chip-level wiring'19874,671,851'Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique'19874,648,937'Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer'19874,641,170'Self-aligned lateral bipolar transistors'19874,583,106'Fabrication methods for high performance lateral bipolar transistors'19864,551,906'Method for making self-aligned lateral bipolar transistors'19854,546,536'Fabrication methods for high performance lateral bipolar transistors'19854,544,576'Deep dielectric isolation by fused glass'19854,521,952'Method of making integrated circuits using metal silicide contacts'19854,506,435'Method for forming recessed isolated regions'19854,507,171'Method for contacting a narrow width PN junction region'19854,492,717'Method for forming a planarized integrated circuit'19854,464,212'Method for making high sheet resistivity resistors'19844,462,040'Single electrode U-MOSFET random access memory'19844,419,809'Fabrication process of sub-micrometer channel length MOSFETs'19834,419,810'Self-aligned field effect transistor process'19834,356,211'Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon'19824,252,579'Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition'19814,234,362'Method for forming an insulator between layers of conductive material'19804,209,349'Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching'19804,209,350'Method for forming diffusions having narrow dimensions utilizing reactive ion etching'19804,169,000'Method of forming an integrated circuit structure with fully-enclosed air isolation'19794,106,050'Integrated circuit structure with fully enclosed air isolation'19784,090,254'Charge injector transistor memory'19784,070,687'Composite channel field effect transistor and method of fabrication'19784,054,989'High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same'19774,032,058'Beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads'19774,017,883'Single-electrode charge-coupled random access memory cell with impurity implanted gate region'19773,997,963'Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads'19763,972,754'Method for forming dielectric isolation in integrated circuits'19763,943,542'High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–1990Patents assigned to IBM (34)· patent assignee history
1976–1990Based in Poughkeepsie, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 34 | 1976–1990 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 34 | 1976–1990 |