Inventor
Zeev Sperber
Inventor
Zichron Yaakov, IL
Overview
Patents· 136 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing80%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
G06TImage data processing or generation, in general4%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
G06NComputing arrangements based on specific computational models1%
H03MCoding1%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
H04JMultiplex communication1%
PatentTitleYear
11,093,247Systems and methods to load a tile register pair202111,086,623Systems, methods, and apparatuses for tile matrix multiplication and accumulation202111,080,048Systems, methods, and apparatus for tile configuration202111,068,263Systems and methods for performing instructions to convert to 16-bit floating-point format202111,068,262Systems and methods for performing instructions to convert to 16-bit floating-point format202111,048,587Apparatus and method for detecting and recovering from data fetch errors202111,036,509Enabling removal and reconstruction of flag operations in a processor202111,036,504Systems and methods for performing 16-bit floating-point vector dot product instructions202111,023,235Systems and methods to zero a tile register pair202111,016,731Using Fuzzy-Jbit location of floating-point multiply-accumulate results202110,990,397Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator202110,963,246Systems and methods for performing 16-bit floating-point matrix dot product instructions202110,942,738Accelerator systems and methods for matrix operations202110,915,421Technology for dynamically tuning processor features202110,877,756Systems, methods, and apparatuses for tile diagonal202010,866,807Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride202010,866,786Systems and methods for performing instructions to transpose rectangular tiles202010,831,477In-lane vector shuffle instructions202010,824,428Apparatuses, methods, and systems for hashing instructions202010,802,567Performing local power gating in a processor202010,754,655Automatic predication of hard-to-predict convergent branches202010,732,970Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset202010,719,316Apparatus and method of improved packed integer permute instruction202010,719,355Criticality based port scheduling202010,649,733Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions202010,623,015Apparatus and method for vector compression202010,572,251Method and apparatus for performing logical compare operations202010,565,283Processors, methods, systems, and instructions to generate sequences of consecutive integers in numerical order202010,521,226Efficient implementation of complex vector fused multiply add and complex vector multiply201910,514,912Vector multiplication with accumulation in large register space201910,514,917In-lane vector shuffle instructions201910,514,918In-lane vector shuffle instructions201910,514,916In-lane vector shuffle instructions201910,509,652In-lane vector shuffle instructions201910,474,463Apparatus and method for down conversion of data types201910,474,459Apparatus and method of improved permute instructions201910,467,011Thread pause processors, methods, systems, and instructions201910,459,728Apparatus and method of improved insert instructions201910,416,997Method and apparatus for performing logical compare operations201910,402,263Accelerating memory fault resolution by performing fast re-fetching201910,324,718Packed rotate processors, methods, systems, and instructions201910,318,244Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions201910,303,471Systems, apparatuses, and methods for performing a double blocked sum of absolute differences201910,223,112Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset201910,223,111Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset201910,223,204Apparatus and method for detecting and recovering from data fetch errors201910,203,955Methods, apparatus, instructions and logic to provide vector packed tuple cross-comparison functionality201910,157,059Instruction and logic for early underflow detection and rounder bypass201810,156,884Local power gate (LPG) interfaces for power-aware operations201810,152,451Scatter using index array and finite state machine201810,146,737Gather using index array and finite state machine201810,146,536Method and apparatus for performing logical compare operations201810,120,684Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory201810,095,522Instruction and logic for register based hardware memory renaming201810,095,516Vector multiplication with accumulation in large register space20189,996,319Floating point (FP) add low instructions functional unit20189,996,127Method and apparatus for proactive throttling for improved power transitions in a processor core20189,996,320Fused multiply-add (FMA) low functional unit20189,946,540Apparatus and method of improved permute instructions with multiple granularities20189,929,745'Apparatus and method for vector compression'20189,904,547'Packed data rearrangement control indexes generation processors, methods, systems and instructions'20189,898,285'Method and apparatus for performing logical compare operations'20189,898,283'Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset'20189,864,602'Packed rotate processors, methods, systems, and instructions'20189,772,674'Performing local power gating in a processor'20179,753,889'Gather using index array and finite state machine'20179,716,646'Using thresholds to gate timing packet generation in a tracing system'20179,696,997'Real time instruction trace processors, methods, and systems'20179,678,751'Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction'20179,672,034'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits'20179,658,850'Apparatus and method of improved permute instructions'20179,639,354'Packed data rearrangement control indexes precursors generation processors, methods, systems, and instructions'20179,626,333'Scatter using index array and finite state machine'20179,619,236'Apparatus and method of improved insert instructions'20179,619,226'Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction'20179,606,770'Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions'20179,588,764'Apparatus and method of improved extract instructions'20179,582,464'Systems, apparatuses, and methods for performing a double blocked sum of absolute differences'20179,542,154'Fused multiply add operations using bit masks'20179,529,592'Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation'20169,519,324'Local power gate (LPG) interfaces for power-aware operations'20169,513,918'Apparatus and method for performing permute operations'20169,495,162'Apparatus and method for performing a permute operation'20169,489,198'Method and apparatus for performing logical compare operations'20169,459,865'Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction'20169,411,395'Method and apparatus to control current transients in a processor'20169,396,056'Conditional memory fault assist suppression'20169,292,362'Method and apparatus to protect a processor against excessive power usage'20169,274,752'Leading change anticipator logic'20169,268,565'Method and apparatus for performing logical compare operations'20169,262,163'Real time instruction trace processors, methods, and systems'20169,229,524'Performing local power gating in a processor'20169,170,813'Method and apparatus for performing logical compare operations'20159,092,226'Efficient parallel floating point exception handling in a processor'20159,043,379'Method and apparatus for performing logical compare operation'20159,037,627'Method and apparatus for performing logical compare operations'20159,037,626'Method and apparatus for performing logical compare operations'20158,972,697'Gather using index array and finite state machine'20158,914,617'Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register'20148,914,430'Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions'20148,914,613'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits'20148,909,988'Recoverable parity and residue error'20148,879,725'Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation'20148,706,789'Performing reciprocal instructions with high accuracy'20148,694,758'Mixing instructions with different register sizes'20148,606,841'Method and apparatus for performing logical compare operation'20138,600,049'Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation'20138,380,780'Method and apparatus for performing logical compare operations'20138,194,854'Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation'20128,103,858'Efficient parallel floating point exception handling in a processor'20128,082,430'Representing a plurality of instructions with a fewer number of micro-operations'20118,078,836'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits'20117,958,336'System and method for reservation station load dependency matrix'20117,958,181'Method and apparatus for performing logical compare operations'20117,921,280'Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array'20117,882,325'Method and apparatus for a double width load using a single width load port'20117,721,076'Tracking an oldest processor event using information stored in a register and queue entry'20107,451,294'Apparatus and method for two micro-operation flow using source override'20087,430,656'System and method of converting data formats and communicating between execution units'20087,389,406'Apparatus and methods for utilization of splittable execution units of a processor'20087,365,753'Texture engine state variable synchronizer'20087,213,136'Apparatus and method for redundant zero micro-operation removal'20077,206,921'Micro-operation un-lamination'20077,202,871'Texture engine memory access synchronizer'20077,167,989'Processor and methods to reduce power consumption of processor components'20077,162,614'Elimination of potential renaming stalls due to use of partial registers'20077,076,614'System and method for optimizing bus bandwidth utilization by grouping cache write-backs'20067,020,789'Processor core and methods to reduce power by not using components dedicated to wide operands when a micro-instruction has narrow operands'20066,947,053'Texture engine state variable synchronizer'20056,944,720'Memory system for multiple data types'20056,920,546'Fusion of processor micro-operations'20056,781,588'Texture engine memory access synchronizer'20046,724,391'Mechanism for implementing Z-compression transparently'20046,580,427'Z-compression mechanism'20036,557,083'Memory system for multiple data types'20036,397,297'Dual cache with multiple interconnection operation modes'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to INTEL CORP (136)· patent assignee history
2002–2016Based in Zichron Yakov, IL· patent location history
2003–2021Based in Zichron Yaakov, IL· patent location history
2011–2020Patents assigned to SPERBER ZEEV (39)· patent assignee history
2011–2020Patents assigned to VALENTINE ROBERT (23)· patent assignee history
2012–2020Patents assigned to GRADSTEIN AMIT (23)· patent assignee history
2016–2018Patents assigned to OULD-AHMED-VALL ELMOUSTAPHA (11)· patent assignee history
2017Based in Haifa, IL· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 136 | 2002–2021 |
| SPERBER ZEEVself | 39 | 2011–2020 |
| GRADSTEIN AMIT | 23 | 2012–2020 |
| VALENTINE ROBERT | 23 | 2011–2020 |
| OULD-AHMED-VALL ELMOUSTAPHA | 11 | 2016–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Zichron Yaakov, IL | 129 | 2003–2021 |
| Zichron Yakov, IL | 4 | 2002–2016 |
| Haifa, IL | 1 | 2017 |