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Inventor

Subramaniam Maiyuran

Inventor
Gold River, CA, US

Overview

46→
Patents
2000–2019
Patent span
Physics
Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing69%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
G11CStatic stores5%
H03KPulse technique5%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
G06TImage data processing or generation, in general2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
10,359,834Graphics processor sub-domain voltage regulation20199,612,835'MFENCE and LFENCE micro-architectural implementation method and system'20179,563,263'Graphics processor sub-domain voltage regulation'20179,471,118'Uncore thermal management'20169,383,998'MFENCE and LFENCE micro-architectural implementation method and system'20169,342,310'MFENCE and LFENCE micro-architectural implementation method and system'20169,336,008'Shared function multi-ported ROM apparatus and method'20169,098,268'MFENCE and LFENCE micro-architectural implementation method and system'20158,959,314'MFENCE and LFENCE micro-architectural implementation method and system'20158,700,937'Uncore thermal management'20148,448,010'Increasing memory bandwidth in processor-based systems'20138,171,261'Method and system for accessing memory in parallel computing using load fencing instructions'20128,065,555'System and method for error correction in cache units'20117,958,284'Multi-channel fractional clock data transfer'20117,694,161'Uncore thermal management'20107,689,772'Power-performance modulation in caches using a smart least recently used scheme'20107,457,917'Reducing power consumption in a sequential cache'20087,155,574'Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory'20067,136,984'Low power cache architecture'20067,136,992'Method and apparatus for a stew-based loop predictor'20067,124,277'Method and apparatus for a trace cache trace-end predictor'20066,898,674'Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers'20056,889,291'Method and apparatus for cache replacement for a multiple variable-way associative cache'20056,885,378'Method and apparatus for the implementation of full-scene anti-aliasing supersampling'20056,845,432'Low power cache architecture'20056,842,180'Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor'20056,801,208'System and method for cache sharing'20046,772,291'Method and apparatus for cache replacement for a multiple variable-way associative cache'20046,735,712'Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains'20046,718,440'Memory access latency hiding with hint buffer'20046,678,810'MFENCE and LFENCE micro-architectural implementation method and system'20046,665,775'Cache dynamically configured for simultaneous accesses by multiple computing engines'20036,651,151'MFENCE and LFENCE micro-architectural implementation method and system'20036,643,745'Method and apparatus for prefetching data into cache'20036,604,162'Snoop stall reduction on a microprocessor external bus'20036,546,462'CLFLUSH micro-architectural implementation method and system'20036,526,499'Method and apparatus for load buffers'20036,507,219'Charge sharing and charge recycling for an on-chip bus'20036,438,658'Fast invalidation scheme for caches'20026,356,270'Efficient utilization of write-combining buffers'20026,356,115'Charge sharing and charge recycling for an on-chip bus'20026,216,215'Method and apparatus for senior loads'20016,205,520'Method and apparatus for implementing non-temporal stores'20016,175,253'Fast bi-directional tristateable line driver'20016,122,715'Method and system for optimizing write combining performance in a shared buffer structure'20006,073,210'Synchronization of weakly ordered write combining operations using a fencing mechanism'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2019Patents assigned to INTEL CORP (46)· patent assignee history
2000–2003Based in Fair Oaks, CA, US· patent location history
2002–2019Based in Gold River, CA, US· patent location history
2010–2014Based in Goldriver, CA, US· patent location history
2011–2017Patents assigned to MAIYURAN SUBRAMANIAM (9)· patent assignee history
2012–2017Patents assigned to PALANCA SALVADOR (5)· patent assignee history
2012–2017Patents assigned to QAWAMI SHEKOUFEH (5)· patent assignee history
2012–2017Patents assigned to FISCHER STEPHEN A (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP462000–2019
MAIYURAN SUBRAMANIAMself92011–2017
PALANCA SALVADOR52012–2017
QAWAMI SHEKOUFEH52012–2017
FISCHER STEPHEN A42012–2017
Locations
LocationPatentsSpan
Gold River, California, US322002–2019
Fair Oaks, California, US102000–2003
Goldriver, California, US42010–2014