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Inventor

Paul Campbell

Inventor
Oakland, CA, US

Overview

22→
Patents
1996–2013
Patent span
Physics
Primary field (CPC G)

Patents· 22 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing61%
B82YSpecific uses or applications of nanostructures7%
G09GArrangements or circuits for control of indicating devices using static means to present variable information7%
G06TImage data processing or generation, in general4%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
8,518,816'Method for making electrical interconnections with carbon nanotubes'20138,389,368'Method for producing a conductive nanoparticle memory device'20138,381,223'Method and apparatus for dynamic allocation of processing resources'20137,987,465'Method and apparatus for dynamic allocation of processing resources'20117,661,107'Method and apparatus for dynamic allocation of processing resources'20107,228,404'Managing instruction side-effects'20077,047,394'Computer for execution of RISC and CISC instruction sets'20066,934,832'Exception mechanism for a computer'20056,886,090'Method and apparatus for virtual address translation'20056,594,750'Method and apparatus for handling an accessed bit in a page table entry'20036,571,315'Method and apparatus for cache memory management'20036,526,459'Allocation of input/output bus address space to native input/output devices'20036,452,599'Method and apparatus for generating a specific computer hardware component exception handler'20026,418,524'Method and apparatus for dependent segmentation and paging processing'20026,393,522'Method and apparatus for cache memory management'20026,385,712'Method and apparatus for segregation of virtual address space'20026,332,184'Method and apparatus for modifying memory accesses utilizing TLB entries'20016,324,635'Method and apparatus for address paging emulation'20016,301,648'Method and apparatus for processing memory accesses utilizing a TLB'20016,249,288'Multi thread display controller'20015,664,154'M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location\'s dirty bit indicates a write-back'19975,486,844'Method and apparatus for superimposing displayed images'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996Based in Berkeley, CA, US· patent location history
1997–2013Based in Oakland, CA, US· patent location history
2001–2007Patents assigned to ATI INT SRL (14)· patent assignee history
2010–2011Patents assigned to ADVANCED MICRO DEVICES INC (2)· patent assignee history
2013Patents assigned to BASSET JEAN-MARIE (2)· patent assignee history
2013Patents assigned to CAMPBELL PAUL (2)· patent assignee history
2013Patents assigned to CENTRE NAT RECH SCIENT (2)· patent assignee history
2013Based in Middlesbrough, GB· patent location history
2013Based in Lyon, FR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ATI INT SRL142001–2007
ADVANCED MICRO DEVICES INC22010–2011
BASSET JEAN-MARIE22013
CAMPBELL PAULself22013
CENTRE NAT RECH SCIENT22013
Locations
LocationPatentsSpan
Oakland, California, US191997–2013
Middlesbrough, GB12013
Lyon, FR12013
Berkeley, California, US11996